REGISTER STACKING IN A COMPUTER auxiliary registers. Each general purpose register and its
SYSTEM corresponding set of auxiliary registers form a register stack.
For example, a register stack is comprised of R0, and
This is a continuation of application Ser. No. 07/886.966 RO^RO". Similarly, other register stacks for each general
filed May 21, 1992. and now abandoned. 5 purpose register are provided. From the perspective of the
CPU and processor instructions executing therein, each
BACKGROUND OF THE INVENTION register stack is identified only by the identity of the corre
1 Field of the Invention sponding general purpose register (i.e. R0-R7 ). Thus, no
'. „ ., „ additional register identification bits are required in proces
The present invention relates to the field of computer 1Q sor instructions
system or processor architectures. Specifically, the present „ , , , , , .
invention pertains to the use of general purpose registers in t \set of re8\sters * tte»n« level in each of the register
a processor architecture. stacks 18 termed a agister level. For example, a register level
is comprised of R0 -R7 . Another register level is com
Z. mor Art prised of registers R0-R7. In general, register levels com
Most modem computers provide a register set for the 15 prise registers from RiT-RT" where m=0. n.
manipulation of data by a central processing unit (CPU). For ^ n of the additiolla] auxiliary registers, a register
example, the 80386 rmcroprocessor manufactured by Inte set sdect st m is ^ in ^ ^ ^ fe^ster
Corporation of Santa Clara, Calif, provides eight general se, sdec, st ^ is a programmabie register used for
purpose registers and various processing instructions for the st0 of a yalue mat identifles the cmrentl actiye
manipulating data in those registers. The use of these 20 register level. The register set select storage area is loaded
registers and the associated processing instructions provides usin ^ additional processor instructions provided as part
a high speed means for manipulating data. The number of of ^ nt invention ^ ister set ^ stor „,
clock cycles required to access information stored in a is connected t0 a register set switch. ^ register set switch
general purpose register is much less than the number of fa used fof selectin a ^ ^ to me register ievel specified
cycles required to access information in a memory, such as 25 by me register set select storage ^ ^ register set sdect
a dynamic random access memory (DRAM). storage ^ is loaded with a yalue denoted me register stack
Currently, many programs require more registers than are pointer. For example, if the register set select storage area is
provided by current computer architectures. In many cases, loaded with a value of 2. the third register level is selected
the code generated by high level prograrnming languages the register set switch enables access to any of the
(i.e., C, FORTRAN, or ADA) requires the use of more 30 registers in the third register level. Specifically, this register
registers than the architecture provides. If enough general ievel includes registers RO2, Rl2 R72. Subsequent to the
purpose registers are not available, data must be spilled to programming of the register set select storage area and the
main memory. Access to main memory, however, is signifi- corresponding action by the register set switch, any register
cantly slower than moving data between general purpose instructions executed by the CPU will operate upon the
registers. Requiring a CPU to write information to main 35 registers in the register level specified by the register set
memory and then later read values back from memory select storage area.
significantly slows the operation of the computer. As part of ^ present ^Q register stack
It is advantageous to have a greater number of general manipulation instructions are provided as extensions to the
purpose registers for a particular computer architecture. existing instruction set. These instructions, denoted herein as
However, software operating on the computer system must push register or PUSHREG and pop register or POPREG.
be significantly modified to take advantage of the additional are executed by the CPU. The PUSHREG instruction is used
registers. Additionally, by increasing the number of general to push the register stack pointer down one level. This is
purpose registers provided in a computer architecture, (he accomplished by incrementing the value contained within
task of managing register allocation becomes more difficult. ^ the register set select storage area. Conversely, the POPREG
In conventional computers, the identification of registers instruction is used to move the register stack pointer up one
is encoded into a field of bits within register manipulation register level. In a alternative embodiment of the present
instructions. These register encodings identify the register or invention, the POPREG and PUSHREG instructions include
registers that are manipulated by the instruction. Typically. an argument that specifies the single register stack that is
however, a limited number of bits is provided for each 5Q manipulated. In this embodiment, only the specified register
instruction. Thus, a limited number of bits is provided for stack is pushed using the PUSHREG instruction or popped
encoding register identities in instructions. In conventional using the POPREG instruction.
computer systems, therefore, the number of registers pro- jjj another embodiment of the present invention, register
vided by the computer system architecture is limited by the stack underflow or overflow conditions are trapped using
size of the instruction format. 55 ^ handling process. If execution of a PUSHREG inshruc
Thus, an improved computer system architecture provid- tion is attempted when all auxiliary register levels have been
ing an expanded register set is needed. previously allocated (i.e. a full register stack), a processor a
trap occurs on this register stack overflow condition.
SUMMARY OF THE INVENTION Conversely, if a POPREG instruction is executed when none
The present invention provides an expanded register set 60 of the auxiliary registers have been previously allocated (i.e.
by employing transparent register stacks for each general an empty register stack), a processor trap occurs on the
purpose register. register stack underflow condition.
The improved computer system architecture of the present In a further improvement of the present invention, task
invention comprises a central processing unit (CPU) and a switching is implemented using a plurality of register stacks
plurality of general purpose registers R0-R7 coupled via a 65 each associated with a frame. Each frame defines the context
set of data lines. In addition, each general purpose register in which an associated task is operating. A task switch is
RG-R7 has associated with it and coupled to it a stack of implemented by simply loading a new frame value (i.e.