MULTIPLE ARRAY ARCHITECTURE FOR
ANALOG OR MULTI-BIT-CELL MEMORY
1. Field of the Invention
This invention relates to non-volatile semiconductor memory capable of storing an analog value or multiple bits per memory cell.
2. Description of Related Art
A typical electrically erasable non-volatile memory contains a memory array including hundreds or thousands of rows of memory cells and hundreds or thousands of columns of memory cells, where each memory cell contains a transistor such as a floating gate or split-gate transistor having a programmable threshold voltage. The threshold voltage of a memory cell (or a transistor within the memory cell) indicates a stored value and is programmed by applying appropriate programming voltages to the control gate, source, and drain of the memory cell. Depending on the resolution of read and write circuits which read and write threshold voltages, non-volatile memory can store one bit, an analog value, or a multi-bit value per memory cell.
In a typical non-volatile memory architecture, each row of memory cells in a memory array has a row (or word) line coupled to control gates of the memory cells in the row. and each column of memory cells has a column (or bit) line coupled to drains of the memory cells in the column. Sources of the memory cells in an array may be connected in a variety of ways. For example, a virtual ground array often has neighboring columns of memory cells that share a column line so that each column line in a virtual ground array is coupled to the drains of memory cells in one column and to the sources of memory cells in the neighboring column. For flash memory, sources of all memory cells in an erasable sector are coupled to a source line for the sector. Accessing memory cells for erase, write, or read operations applies appropriate voltages to the row, column, and source lines coupled to the memory cell or cells to be erased, written, or read. When programming (or writing to) a selected memory cell, programming voltages applied to selected row, column, and source lines for a sufficient period change the threshold voltage of the memory cell coupled to those lines.
A problem in non-volatile memories is that voltages applied to row and column lines of memory cells selected for a write or erase operation can disturb or change the threshold voltages of memory cells in (lie same columns or rows as the selected memory cells. The accumulated threshold voltage disturbances from writing to hundreds or thousands of memory cells in the same row or column can significantly change the threshold voltage of a memory cell and the value stored in the memory cell. This problem is particularly significant for large memory arrays which have more memory cells per row and column. The problem is also significant in analog or multilevel memories where a relatively small variation in a threshold voltage changes the value stored. Accordingly, methods and architectures for reducing the write and erase disturb in analog and multilevel memories are sought.
In accordance with the invention, a memory architecture partitions memory cells of a memory into multiple memory arrays where each memory array has local lines that are coupled to memory cells in the memory array and electri
cally isolated from local lines of other arrays. Continuous global row, column, and/or source lines cross the memory arrays. The memory additionally includes global decoders that decode an address signal and apply operating voltages
5 to the global line or lines corresponding to the selected memory cell or cells being accessed. Local decoders select an array containing the selected memory cell and connect the global lines to the local lines of the memory array containing the selected memory cell while the local lines of
10 other memory arrays are disconnected from the global lines to avoid disturbance that would result from the operating voltage being applied to the local lines (i.e., to memory cells.)
Embodiments of the invention include but are not limited 15 to analog and multilevel memory which are particularly sensitive to disturbance of the threshold voltage. Dividing such memories into multiple arrays reduces the accumulated disturb by a factor about equal to the number of arrays. Separation of decoding circuitry into global and local decod20 ers reduces the overhead when compared with a memory having multiple arrays where each array has self-sufficient decoders.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a multiple array architecture in accordance with an embodiment of the invention where global decoders are at the perimeter of an array of memory arrays.
FIG. 2 shows a multiple array architecture in accordance 30 with an embodiment of the invention where global decoders are within an array of memory arrays.
FIG. 3A shows a multiple array architecture and a local decoder for a memory including two arrays in a column. FIG. 3B shows a layout for integrated circuit structures 35 forming a portion of the local decoder in the memory of FIG. 3A.
FIG. 4 shows a multiple array architecture and local decoder for a memory including two arrays in a row. ^ FIG. 5 shows a multiple array architecture and local decode circuitry for a memory including two rows and two columns of memory arrays.
FIG. 6 shows a multiple array architecture in accordance with an embodiment of the invention where source line 45 voltages in unselected sectors are biased to reduce programming disturb.
Use of the same reference symbols in different figures indicates similar or identical items.
In accordance with an aspect of the invention, an analog or multilevel memory includes multiple arrays of memory cells where each memory array has local row lines, local
55 column lines, and/or local source lines coupled to local decoders. Local row, column, and source lines of the different arrays are electrically separated to reduce the number of memory cells in the same row or column as memory cells being program and reduce the number of threshold voltage
60 disturbances. Accordingly, the multiple array architecture reduces the accumulated threshold voltage disturb when compared to a memory architecture having a single larger array. In accordance with a further aspect of the invention, the memory includes global decoders such as a global row
65 decoder and/or a global column decoder with global row lines and/or global column lines for multiple arrays. The local column or row decoders connect the global column or