An electrically erasable programmable read only memory block is provided which includes a plurality of rows of 2-bit non-volatile memory cells. Each of the memory cells has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. Each pair of...http://www.google.com/patents/US20010021126?utm_source=gb-gplus-sharePatent US20010021126 - EEPROM array using 2 bit non-volatile memory cells and method of implementing same
EEPROM array using 2 bit non-volatile memory cells and method of ...
