POWER-UP CALIBRATION OF CHARGE
FIELD OF THE INVENTION This application relates to calibration of analog-to-digital converters, and more particularly to circuitry that automatically initiates calibration of a charge redistribution analogto-digital converter on start up, once it has reached its normal operating conditions.
BACKGROUND OF THE INVENTION
It is known to construct charge redistribution analog-todigital converters (ADC's) using integrated circuit technology. These integrated ADC's trap a charge proportional to the analog voltage to be measured, and then gauge the amount of charge trapped by testing it against differentlysized capacitors in an array. They tend to remain linear over their operating temperature range because the capacitance of capacitors made using integrated circuit technology usually does not to vary much in response to temperature changes. In addition, because the capacitors are in parallel, only differences in their temperature coefficients will affect linearity, and these differences can be significantly reduced by closely integrating the arrays.
These performance characteristics are not usually available immediately after supplying power to the part. Typically, the part must be allowed to settle before it reaches normal operating conditions, which can be defined as a state where the device operates consistently within a certain range of performance parameters, such as accuracy, linearity, or offset ranges. Before the part reaches this condition, its performance is affected by transient effects within the part, such as the charging of capacitors, or possibly the warming of circuit components.
It is known to provide calibration circuitry for these converters to compensate for manufacturing tolerances, drifts, or the like. For example, the calibration circuitry can include a switched array of capacitors that acts like a variable capacitor. This type of array can be connected in parallel with a capacitor in the ADC to allow adjustment of the total capacitor capacitance until it reaches a desired value. Typically, initiating a calibration operation involves asserting a signal on a calibration control pin, or providing a calibration command to a control register within the part via the part's bus interface, and calibration is usually not initiated until the part has been powered up for a certain interval, to allow the converter to reach its normal operating conditions.
Analog-to-digital converters can also include "shutdown" circuitry, which reduces power consumption to a minimum. When the converter is in shutdown mode, the analog circuitry in the converter receives only very small leakage currents. Upon returning from shutdown mode to normal operation, the ADC circuitry should generally be allowed to again reach normal operating conditions before relying on conversion values, to ensure accurate results.
Present converters usually require that the system designer provide circuitry and/or software that initiates power-up calibration. In addition, if the user intends to immediately place the part in shutdown mode after powerup, the user must typically first initiate calibration of the part and then provide a shutdown command to the part.
SUMMARY OF THE INVENTION Generally, the invention features using a power-up delay circuit on an analog/digital converter integrated circuit (i.e.,
an analog-to-digital converter or a digital-to-analog converter) to generate a signal delayed from power-up, and initiating a calibration of the converter upon detecting the delayed signal. In preferred embodiments, calibration can
5 also be initiated in response to a signal on a calibration input pin of the integrated circuit, and the duration of the delay can be derived from a reference (e.g., by charging an external capacitor with it) or from the duration of a calibration operation. Circuitry can be provided to automatically place
10 the circuit in an operating mode upon power-up that keeps the integrated circuit in shutdown mode when it is not converting or calibrating.
The circuitry according to the invention is advantageous in that the system that incorporates it does not have to
15 provide a power-up calibration command. In addition, the user may benefit from an automatic shutdown on power-up mode, which further reduces system requirements. The circuitry therefore permits the user to obtain the advantages of a calibrated charge-redistribution ADC without having to
20 allocate as much design time or system resources to calibration issues as might otherwise be required. If desired, the user may even be able to ignore calibration issues altogether, and think of a thus-calibrated ADC as a low power, high accuracy black box that simply supplies digital voltage
25 values at its output.
By providing power-up calibration control circuitry on-chip, the power-up delay can be determined by circuitry that is influenced by the same factors as the converter itself. The power-up delay can therefore be closely matched to the
30 time required for the converter to reach normal operating conditions. This allows the circuit to become operable as quickly as possible, without sacrificing accuracy.
In one embodiment of the invention, there need be no external calibration pin at all, which can reduce both con
35 verier circuit costs and system costs.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram illustrating a charge redistribution analog-to-digital converter integrated circuit with 40 power management and power-up control circuitry according to one embodiment of the invention;
FIG. 2 is a schematic diagram of a one-shot circuit for use in the power-up control circuit of FIG. 1;
FIG. 3a is a waveform diagram presenting the voltage at 45 the buffer input in the power-up circuit of FIG. 1 during power-up;
FIG. 3b is a waveform diagram presenting the voltage at the buffer output in the power-up circuit of FIG. 1 during power-up;
50 FIG. 3c is a waveform diagram presenting the voltage at the first one-shot output in the power-up circuit of FIG. 1 during power-up;
FIG. 3d is a waveform diagram presenting the voltage at the second one-shot output in the power-up circuit of FIG. 1 during power-up;
FIG. 4a is a more detailed view of the voltage of FIG. 3a over a shortened range;
FIG. 4b is a more detailed view of the voltage of FIG. 3b 60 over a shortened range;
FIG. 4c is a more detailed view of the voltage of FIG. 3c over a shortened range;
FIG. 4d is a more detailed view of the voltage of FIG. 3d over a shortened range; 65 FIG. 5 is a schematic of an alternative power-up control circuit according to the invention for use in the integrated circuit of FIG. 1;