METHOD AND SYSTEM FOR MEASURING
SIGNAL PROPAGATION DELAYS USING
THE DUTY CYCLE OF A RING
CROSS REFERENCE TO RELATED
This application is a continuation-in-part of U.S. patent application Ser. No. 08/710,465, U.S. Pat. No. 5,790,479, entitled "Method for Characterizing Interconnect Timing Characteristics Using Reference Ring Oscillator Circuit," by Robert O. Conn, filed Sep. 17, 1996 [docket X-252]. This application is related to application Ser. No. 09/114,369, entitled "Method and System for Measuring Signal Propagation Delays Using Ring Oscillators," by Robert D. Patrie, Robert W. Wells, Steven P. Young, Christopher H. Kingsley, Daniel Chung, and Robert O. Conn filed herewith [docket X-252-3P], and U.S. patent application Ser. No. 09/115,204, entitled "Built-in Self Test Method For Measuring Clock to Out Delays," by Robert W. Wells, Robert D. Patrie, and Robert O. Conn filed herewith [docket X-252-4P]. The foregoing applications are incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates generally to methods and circuit configurations for measuring signal propagation delays, and in particular for measuring signal propagation delays through integrated circuits.
Integrated circuits (ICs) are the cornerstone of myriad computational systems, such as personal computers and communications networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that guarantee superior speed performance. This leads IC manufacturers to carefully test the speed performance of their designs.
FIG. 1 depicts a conventional test configuration 100 for determining the signal propagation delay of a test circuit 110 in a conventional IC 115. A tester 120 includes an output lead 125 connected to an input pin 130 of IC 115. Tester 120 also includes an input line 135 connected to an output pin 140 of IC 115.
Tester 120 applies an input signal to input pin 130 and measures how long the signal takes to propagate through test circuit 110 to output pin 140. The resulting time period is the timing parameter for the path of interest. Such parameters are typically published in literature associated with particular ICs or used to model the speed performance of circuit designs that employ the path of interest.
Conventional test procedures are problematic for at least two reasons. First, many signal paths within a given IC cannot be measured directly, leading to some speculation as to their true timing characteristics. Second, testers have tolerances that can have a significant impact on some measurements, particularly when the signal propagation time of interest is short. For example, if the tester is accurate to one nanosecond and the propagation delay of interest is measured to be one nanosecond, the actual propagation delay might be any time between zero and two nanoseconds. In such a case the IC manufacturer would have to list the timing parameter as two nanoseconds, the worst-case scenario. If listed timing parameters are not worst-case values, some designs may fail. Thus, IC manufacturers tend to add
relatively large margins of error, or "guard bands," to ensure that their circuits will perform as advertised. Unfortunately, this means that those manufacturers will not be able to guarantee their full speed performance, which could cost 5 them customers in an industry where speed performance is paramount.
Programmable logic devices (PLDS) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic
10 functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks, or CLBs, that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable logic may be
15 customized by loading configuration data into internal configuration memory cells that, by determining the states of various programming points, define how the CLBs, interconnections, and IOBs are configured.
Each programming point, CLB, interconnection line, and
20 IOB introduces some delay into a signal path. The many potential combinations of these and other delay-inducing elements make timing predictions particularly difficult. FPGA designers use circuit models, called "speed files," that include delay values or resistance and capacitance values for
25 the various delay-inducing elements that can be combined to form desired signal paths. These circuit models are then used to predict circuit timing for selected FPGA configurations.
Manufacturers of ICs, including FPGAs, would like to guarantee the highest speed timing specifications possible
30 without causing FPGAs to fail to meet timing specifications. More accurate measurements of circuit timing allow IC manufacturers to use smaller guard bands to ensure correct device performance, and therefore to guarantee higher speed performance. There is therefore a need for a more accurate
35 means of characterizing IC speed performance.
The present invention addresses the need for an accurate means of characterizing IC speed performance. The inven
40 tive circuit is particularly useful for testing programmable logic devices, which can be programmed to include a majority of the requisite test circuitry.
In accordance with the invention, a PLD is configured to implement a free-running ring oscillator within the elements
45 of the PLD to be tested. That is, the PLD is programmed to form a loop through PLD elements to be tested, with an odd number of inversions in the loop so that a signal switches on every cycle through the loop. The oscillator then automatically provides its own test signal that includes alternating
50 rising and falling signal transitions, or edges, on the testcircuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. This average period is then related to the average signal propagation delay through the test circuit.
55 Signal paths often exhibit different propagation delays for falling and rising edges, due to imbalanced driver circuits, for example. The trouble with providing average propagation delays is that the worst-case delay is generally greater than the average. Consider, for example, the case where a
60 signal path delays falling edges by 2 nanoseconds and rising edges by 3 nanoseconds. The average, 2.5 nanoseconds, is shorter than the worst-case delay associated with rising edges. Unfortunately, the average delay does not indicate whether the delays associated with falling and rising edges
65 are different. Thus, when only the average delay is being measured, a conservative guard band must be added to the average delay.