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FIELD OF THE INVENTION
This invention relates to clock generation and partic- 5 ularly to the generation of a clock signal on an integrated circuit.
BACKGROUND OF THE INVENTION
There have been recently dramatic increases in the 10 performance of integrated circuit graphic systems, resulting in the requirement for ever increasing data rates. Data rates in mainstream graphics workstations have increased from 25 MHz to over 100 MHz, and future increases are probable. 15
Currently, information destined for screen output is stored in a block of memory called a frame store which periodically outputs its information in a serial fashion at a rate called the pixel dot rate. This serial information can be manipulated by graphics hardware at the pixel 20 dot rate and is ultimately converted by a digital-toanalogue converter (DAC) to analogue voltages which can control the electron guns in a cathode ray tube (CRT).
To utilise readily available and cheap memory tech- 25 nology which cannot operate at such high speeds, the aforementioned frame store is split up into a plurality of smaller frame stores which operate more slowly and in parallel. Pixel data from the frame stores is outputted in parallel streams down a pipeline. These pixel streams 30 are combined by a multiplexor into one high speed serial stream, upstream of the DAC.
Generally such combination involves a high speed clock to control this multiplexor. Any graphics hardware required to operate on the high speed serial pixel 35 stream will also have to be controlled by this high speed clock. It is known to provide the multiplexor combining the multiple pixel stream on the same silicon chip as a high speed sequential graphics device even though an external high speed clock at the pixel dot rate fre- 40 quency, has also had to be supplied to control both. This produces a synchronisation problem which is difficult to solve, because the low rate data entering the graphics device is not correlated with the high speed clock. Even if the low rate data is controlled by a signal derived 45 from the high speed clock, for example by using a frequency divider, delays are such that at these high frequencies this has to be viewed as uncorrelated. In addition to this problem extra costs are incurred to generate the high speed clock. 50
More generally, it is often required to take into a silicon chip several data streams at lower frequencies. Once combined into a single stream this data can be used as the input to another part of the chip. Both stages require the input of an external clock which is at the 55 highest frequency that occurs on the chip. This is expensive and produces synchronisation problems.
It is an object of the present invention to solve the problem of synchronising incoming data at a low rate with an integrated circuit processing device utilising 60 that data at a higher rate.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided an integrated circuit comprising: a 65 multiplexor connected to receive incoming data at a first rate and controllable by a high rate clock signal to output that data serially at a second, higher rate; a pro
cessing device coupled to receive data output from the multiplexor at the higher rate and controllable by a high rate clock signal to process that data; and clock generation circuitry connected to receive a first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor.
By utilising clock generation circuitry which is part of the integrated circuit device to produce the high rate clock signal from the first clock signal used to regulate the incoming data it is possible to ensure that the operation of the processing device will be synchronised to the data rate of the data which it is processing.
Thus, this invention relates in its preferred embodiment to the provision on chip of a multiplexor to take in slower parallel streams, a higher speed processing device, and a clock acceleration circuit to take in an input of a lower frequency and generate the required high frequency clock to control the rest of the chip. To ensure synchronisation, the lower frequency input used is the same frequency used to control the incoming data streams. Hence no such high frequency is now required to be supplied from an external source. Because all high frequency signals only exist within the bounds of this one chip (with the exception of the output which only goes straight to a CRT) then all timing and synchronisation problems can be solved by the chip designer, not the system designer.
A user of the integrated circuit, which will be sold in the form of a chip, need only provide a single, low rate clock and does not need to concern himself with the clock speed and synchronisation in the integrated circuit. This offers considerable attraction to purchasers of integrated circuit chips.
According to another aspect of the present invention there is provided clock generation circuitry for providing from a first clock signal a second clock signal at a different rate, the circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time interval after receiving a trigger signal from the previously connected delay device; control means common to said delay devices for controlling said predetermined time interval; and output means coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.
It will be appreciated that the term clock signal is used to denote any periodic function and is not restrictive of the application to which such a function might be put.
This clock generation circuitry is particularly suitable for use in the first aspect of the present invention, when the second clock signal is at a higher rate than the first clock signal.
Preferably the control means is connected in a feedback loop so as to be responsive to an error signal resulting from comparison of the first clock signal with the output signal of the last connected delay device. By incorporating a control system in this way, the output signals of the connected delay devices can be made to occur in a regular fashion between consecutive pulses of the first clock signal.
The output means can be arranged to provide two second clock signals at the same frequency but in antiphase.
Circuitry of this type lends itself well to manufacture in an integrated circuit and obviates the need for an externally provided high rate clock signal. Effectively a first order control system has been created by replacing the voltage controlled oscillator of a phase locked loop 5 with a triggered chain of events. This is easier to control yet stable over a large period of time and consequently more resistant to noise.
The delay devices can be conventional delays or monostables of which numerous examples are known. 10 A preferred delay device however is one devised by the present inventor and comprising a timing circuit and a control circuit, the timing circuit comprising a controllable switch element for receiving a reset signal, capacitive means connected to be charged up when said con- 15 trollable switch element is in a first state, and comparator means connected to receive as a first input signal the voltage across the capacitive means, and as a second input signal a control voltage, and producing as an output a timing signal in dependence on said first and 20 second input signals and the control circuit being connected to receive said timing signal and to provide in response thereto the trigger signal of the delay device and the said reset signal. The control voltage is conveniently derived from said control means of the clock 25 generation circuitry.
Such a monostable provides a greater dynamic range than known delay devices. This is usually limited in practice by the gain of a circuit being too high at some point in its characteristic, causing a sensitivity to noise 30 under particular circumstances which is hard to suppress. Here this has been overcome by making the gain (expressed as the change in said predetermined time interval for a certain change in said control voltage), as constant as possible between the two end points of the 35 required dynamic range. This ensures that the gain is no higher than it needs to be to achieve the required minimum and maximum time intervals. In the preferred embodiment this is achieved by not using, in contrast to conventional delay devices, a low biased MOSFET to 40 limit any currents or to add loads to certain nodes to perform the control of the delay device.
The number of selected delay devices affects the multiplication factor by which the second clock signal differs from the first clock signal. The clock generation 45 circuitry can be manufactured with p delay devices with means for selecting n of the p delay devices (where n=p) for use in generation of the second clock signal. In this way it is unnecessary to decide at the manufacturing stage how many delay devices are required for 50 any specific application.
Where the number p of delay devices is a known, even number, the output means for producing the second clock signals can be designed as a fixed logic array without too much difficulty. However, when an un- 55 known number n of delay devices is to be utilised a more sophisticated arrangement is required. According to one embodiment of the present invention said output means comprises a plurality of generation units connected respectively to receive the output signals of the 60 p delay devices, the generation units being individually connectable to a common output line and each generation unit having three states: a neutral state in which the output line is examined; a negative drive state in which a negative going pulse is driven onto the output line; 65 and a positive drive state in which a positive going pulse is driven onto the output line, the second clock signal thereby being generated on the output line as follows:
prior to receipt of a trigger signal by its associated delay device a generation unit is in its neutral state and when a delay device receives a trigger signal the generation unit associated with that delay device responds to the output signal of that delay device to adopt one of its positive and negative drive states in dependence on the state of the second clock signal just prior to the change of state of that generation unit.
The generation units can also be individually connectable to a second common output line and arranged so that in their negative drive states a positive going pulse is driven onto the second common output line and in their positive drive states a negative going pulse is driven onto the second common output line thereby to generate a clock signal in antiphase to said second clock signal.
For a better understanding of the present invention, and to show how the same can be carried into effect, reference will now be made, by way of example, to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing the principle of on chip clock generation;
FIG. 2 is a schematic diagram showing the principle of an embodiment of the present invention using feedback;
FIG. 3 is a more detailed diagram of the embodiment of the present invention shown in FIG. 2;
FIG. 4 is a timing diagram for the operation of the circuitry of FIG. 3;
FIG. 5 is a schematic diagram of the generation units;
FIG. 6 is a circuit diagram of one generation unit;
FIG. 7 is a graph showing the relationship between change in time interval and changes in the control voltage for different delay devices;
FIG. 8 is a circuit diagram of a delay device in accordance with one embodiment of the invention; and
FIG. 9 is a circuit diagram of the control circuit of FIG. 8.
DESCRIPTION OF THE PREFERRED
FIG. 1 shows components implemented on a single integrated circuit device or chip. A multiplexor 2 receives input data at a normal clock rate, for example 25 MHz. The incoming data latched by a low rate clock signal, is multiplexed into a high rate data stream to be passed to a high speed device 4, for example a graphics processing device. Operation of the multiplexor 2 and the high speed device 4 is controlled in accordance with the principle of the present invention by an on chip clock accelerator 6 which receives the low rate clock signal and generates therefrom a high rate clock signal CLK synchronised with the low rate clock. The signal CLK comprises two signals in antiphase, CLK1 and CLK2.
The basic construction of the clock accelerator is described with reference to FIG. 2. It comprises an input circuit 8 for receiving the low rate clock signal and a plurality of sequentially connected delay devices which are represented in FIG. 2 by the single box 10 connected to the input circuit 8. The output of the sequentially connected delay devices 10 is fed to an error generator 12 which also receives the low rate clock signal from the input circuit 8. The output signal from the error generator 12 is an error signal E which is fed to a loop filter 14 which integrates it to provide a com5
mon control voltage Vc for controlling the plurality of delay devices 10. Operation of the circuit will become clearer as each individual component is described in the following.
Referring now to FIG. 3 the plurality of delay de- 5 vices DO to D5 in the box 10 are shown individually. The first delay device DO is connected to receive the input clock signal from the input circuit 8. The next delay device Dl and subsequent delay devices D2 to D5 are connected in sequence to the first delay device DO. 10 Each delay device acts to generate an output signal at a predetermined time interval after the receipt of a trigger signal. The output signal of each delay device DO to D5 is received by an output means in the form of a buffer 16 which generates two antiphase clock signals in a man- 15 ner to be described hereinafter. The detailed operation of the delay devices will also be described in more detail below. However, referring to FIG. 4, it is noted here that the input signal for the first delay device acts as a trigger signal to cause the first delay device to produce 20 a trigger signal after a predetermined time interval t, in the form of a falling edge. The falling edge triggers the next delay device Dl which acts similarly to produce an output signal after time t. As will become clearer in the following, in the described embodiment the output sig- 25 nal of each delay device is the inverse of its output trigger signal. This is repeated to the last delay device D5. The time intervals t, are controlled by a common voltage signal Vc from the filter 14. The trigger signal output by the last delay device D5 is compared with the 30 next incoming clock pulse, and any phase error E will influence the filter to alter the control voltage Vc and hence the time intervals. In this way, a series of pulses synchronised to the incoming clock signal and of equal length can be produced. 35
It is important to note that the time interval, t, is the same for each delay device, achieved by supplying a common control signal, voltage Vc, to all the delay devices. This is the basis of clock signal production to be described later. 40
The buffer 16 comprises a plurality of generation units, a generation unit being associated with each respective delay device DO to D5. In the buffer each generation unit GO to G5 is connected to drive two common output lines 18, 20 (see FIG. 5). The output 45 lines 18,20 feed a driving unit 22 from whence issue the antiphase clock signals CLK1, CLK2 on respective ones of the output lines 18, 20. Each generation unit GO to G5 is also connected to examine the output signal CLK1. In FIG. 5, two delay devices D4, D5 are shown 50 with their respective associated generation units G4, G5.
The circuit of FIG. 3 has six delay devices. However, it may be desirable to utilise only four or five of these, depending on the required acceleration factor of the 55 clock signal. This is indicated diagrammatically by the dotted arrows in FIG. 3.
Where the number of delay devices is a known, even number, the output means 16 for producing the second clock signal could be designed as a fixed logic array 60 without too much difficulty. However, when an unknown number of delay devices is to be selected, a more sophisticated arrangement is required, utilising the generation units discussed above. Each generation unit is connected to receive the output signal of its associated 65 delay device and to drive appropriate signals onto the common output lines 18, 20. Each generation unit has three states: a neutral state in which the output signal
CLKl is examined; a first drive state in which a negative going pulse is driven onto one of the output lines and a positive going pulse is simultaneously driven onto the other output line; and a second drive state in which the pulses are reversed. The second clock signals are generated in the output lines as follows: prior to receipt of a trigger signal by its associated delay device a generation unit is in its neutral state examining CLKl. When a delay device receives a trigger signal the generation unit associated with that delay device responds to the output signal of that delay device to adopt one of its first and second drive states in dependence on the state of CLKl just prior to the change of state of that generation unit. The length of each pulse is determined by the time interval t, of the delay devices.
The circuitry of each generation unit is shown in FIG. 6. An input n-channel transistor 24 is connected to receive at its gate the output signal of the delay device associated with the generation unit. The output signal is also fed to a first inverter 26 and to the gates of p-channel transistors 28, 30. The output of the first inverter 26 is connected to the gates of n-channel transistors 32, 34. Each p-channel transistor 28,30 forms with a respective n-channel transistor 32, 34 a transmission gate. A pchannel transistor 36 is connected between a voltage supply and the drain of the input transistor 24, the gate of this transistor 36 being fed from the output signal of a second inverter 38 connected to the drain of the input transistor 24. The second inverter 38 feeds a third inverter 40 which in turn feeds a fourth inverter 42. The input of the transmission gate 30, 34 is connected to the output of the third inverter 40 and the input of the transmission gate 28, 32 is connected to the output of the fourth inverter 42. The output of the transmission gate 30,34 is connected to one of the output lines 18 and the output of the transmission gate 28, 32 is connected to the other of the output lines 20. Finally, the source of the input transistor 24 is connected to examine one of the output signals CLKl.
It will be assumed for the purposes of the following explanation that the starting state is such that the clock signal CLKl is high, its counterpart CLK2 is low and the delay device associated with the particular generation unit it is inactive; in other words, the signal applied to the input transistor 24 is high. In these circumstances, the input transistor 24 is "on", its drain (the input of inverter 38) follows the clock signal CLKl and goes high, the output of the inverter 38 hence goes low, the output of the inverter 40 goes high and the output of the inverter 42 goes low. Due to the inverter 26, the transistors 32 and 34 are however "off'. When the delay device associated with the generation unit becomes active and issues its output signal, which is the inverse of the falling edge trigger signal as described earlier, the input transistor 24 is turned "off' while the transistors 32 and 34 are turned "on". That is, the signals at the outputs of the inverters 40 and 42 are connected respectively to the output lines 18 and 20. As discussed above, the output of the inverter 40 is high and the output of the inverter 42 is low. Hence, the clock signal CLKl goes low and its counterpart CLK2 goes high, i.e. the reverse of the states prior to the delay device going active. It is a particular advantage of this invention that two antiphase and perfectly synchronised clock signals are produced without any additional circuitry. That is, it is as easy to produce two antiphase clock signals as it is to produce one. These clock signals and their relationship