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ARRAY OF NON-VOLATILE MEMORY
CELLS WITH FLOATING GATES FORMED
OF SPACERS IN SUBSTRATE TRENCHES
CROSS REFERENCE TO RELATED 5
This application is related to an application Ser. No. 11/533,317, being filed Sep. 19, 2006 by Nima Mokhlesi, entitled "Method of Making an Array of Non-Volatile 10 Memory Cells With Floating Gates Formed of Spacers in Substrate Trenches," publication no. US 2008/0070363 Al, which application is incorporated herein in its entirety by this reference.
This invention relates generally to non-volatile flash memory systems, and, more specifically, to a structure and process of forming arrays of memory cells that utilize sub- 20 strate trenches to reduce the overall size of the arrays.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM (Electrically Erasable and Programmable Read Only 25 Memory) cells. Arrays with either a NOR or a NAND architecture are commonly used. One or more integrated circuit chips containing a memory cell array are commonly combined with a controller chip to form a complete memory system. Alternatively, part or all of the controller function 30 may be implemented on the same chip that contains all or part of the memory cell array.
In one type of NOR array, each memory cell has a "splitchannel" between source and drain diffusions. The floating gate of the cell is positioned over one portion of the channel 35 and the word line (also referred to as a control gate) is positioned over the other channel portion as well as over the floating gate. This effectively forms a cell with two transistors in series, one (the memory transistor) with a combination of the amount of charge on the floating gate and the voltage on 40 the word line controlling the amount of current that can flow through its portion of the channel, and the other (the select transistor) having the word line alone serving as its gate. The word line extends over a row of floating gates. Examples of such cells, their uses in memory systems and methods of 45 manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, and 6,281, 075.
A modification of this split-channel flash EEPROM cell adds a steering gate positioned between the floating gate and 50 the word line. Each steering gate of an array extends over one column of floating gates, perpendicular to the word lines. The effect is to relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of 55 a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the floating gate to a desired level through an electric field (capacitive) coupling between the word line and the floating gate. It is often difficult to perform both of these functions in 60 an optimum manner with a single voltage. With the addition of the steering gate, the word line need only perform function (1), while the added steering gate performs function (2). The use of steering gates in a flash EEPROM array is described, for example, in U.S. Pat. Nos. 5,313,421 and 6,222,762. 65
In one specific type of memory cell that efficiently utilizes integrated circuit area, two floating gates are included, each of
which may be operated in binary (one bit per floating gate) or with multiple programming states (more than one bit per floating gate). The two floating gates are positioned over the substrate channel between source and drain diffusions with a select transistor in between them. A steering gate is included along each column of floating gates and a word line is provided thereover along each row of floating gates. When accessing a given floating gate for reading or programming, the steering gate over the other floating gate of the cell containing the floating gate of interest is raised sufficiently high to turn on the channel under the other floating gate no matter what charge level exists on it. This effectively eliminates the other floating gate as a factor in reading or programming the floating gate of interest in the same memory cell. For example, the amount of current flowing through the cell, which can be used to read its state, is then a function of the amount of charge on the floating gate of interest but not of the other floating gate in the same cell.
Examples of an array with dual floating gate memory cells, and operating techniques therefore, are described in U.S. Pat. Nos. 5,712,180, 6,103,573 and 6,151,248. The dual floating gate memory cell arrays are usually formed entirely on a surface of a semiconductor substrate. However, U.S. Pat. No. 6,151,248 additionally describes, primarily with respect to FIGS. 6 and 7 thereof, memory cells formed in a trench in the substrate surface and along surface areas of the substrate adjacent to the trench. U.S. Pat. No. 6,936,887 also describes an array of memory cells partially formed in substrate trenches.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells in a row direction, across a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, 6,522,580, 6,888,755 and 6,925,007.
There are various programming techniques for causing electrons to travel through the gate dielectric from the substrate onto the floating gate. The most common programming mechanisms are described in a book edited by Brown and Brewer, "Nonvolatile Semiconductor Memory Technology," IEEE Press, section 1.2, pages 9-25 (1998). One technique, termed "Fowler-Nordheim tunneling" (section 1.2.1), causes electrons to tunnel through the floating gate dielectric under the influence of a high field that is established thereacross by a voltage difference between the control gate and the substrate channel. Another technique, channel hot electron injection in the drain region, commonly referred to as "hot-electron injection" (section 1.2.3), injects electrons from the cell's channel into a region of the floating gate adjacent the cell's drain. Yet another technique, termed "source side injection" (section 1.2.4), controls the substrate surface electrical potential along the length of the memory cell channel in a manner to create conditions for electron injection in a region of the channel away from the drain. Source side injection is also described in an article by Kamiya et al., "EPROM Cell with High Gate Injection Efficiency," IEDM Technical Digest, 1982, pages 741-744, and in U.S. Pat. Nos. 4,622,656 and 5,313,421. In a farther programming technique, termed "ballistic injection" high fields are generated within a short channel to accelerate electrons directly onto the charge stor