1
APPARATUS AND METHOD FOR
PERFORMING STATIC TIMING ANALYSIS
OF AN INTEGRATED CIRCUIT DESIGN
RELATED APPLICATION 5
This patent application is related to a U.S. patent application "APPARATUS AND METHOD FOR PERFORMING STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN USING DUMMY EDGE MODEL- 10 ING", Ser. No. 10/777,261 filed on Feb. 12, 2004, which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
15
1. Technical Field
This invention generally relates to integrated circuits, and more specifically relates to static timing analysis of integrated circuit designs.
2. Background Art 20 The proliferation of modern electronics is due in large part
to the development of the integrated circuit. Integrated circuits allow many different circuit elements to be implemented on a single chip. As technology advances, the number of circuit elements on a chip of a given size 25 increases, enhancing the performance and reducing the cost of integrated circuits.
The design of integrated circuits is typically performed in three stages. The first stage is logic design, wherein the desired operation of the integrated circuit is defined. The 30 second stage is logic synthesis, wherein the desired operation is translated into the required circuit elements for a given technology. The third stage is physical design, which assigns the placement of these elements and routing which creates the wire interconnect of these elements on the 35 integrated circuit. Placement defines the location of the circuit elements on the integrated circuit. Routing defines interconnections between circuit elements.
At the logic synthesis stage, a static timing tool is typically used to perform a static timing analysis. Static timing 40 analysis generally takes into account best-case and worstcase delays of various circuit elements, thereby generating a list of problems that need to be corrected. One common static timing tool developed by IBM is known as EinsTimer. EinsTimer is a sophisticated timing tool that performs static 45 timing analysis on an integrated circuit design to identify potential timing problems with the design. EinsTimer includes sophisticated methods for performing the timing analysis. However, EinsTimer makes unduly pessimistic timing assumptions in some cases. As a result, integrated 50 circuit designers must generally account for the pessimistic timing assumptions in a manual fashion. Without a mechanism for improving the pessimistic timing assumptions in known static timing tools, the integrated circuit design industry will have to spend excessive time manually ana- 55 lyzing circuits that are identified as a problem using a static timing tool.
DISCLOSURE OF INVENTION
60
An apparatus and method perform static timing analysis on an integrated circuit design. Certain pessimistic assumptions regarding slack when data launch and clock test signals are on opposite edges and derived from common logic blocks are improved by allowing the designer to identify 65 common logic blocks, to compute the difference between maximum and minimum delays in the common logic blocks,
2
and to improve the slack using this computed difference and a correction factor, thereby accounting for excessive pessimism in the static timing analysis that results from the common logic blocks. The apparatus and method give credit for slack in common blocks automatically, thereby allowing a large number of pessimistic slack values to be automatically corrected and reducing the workload of an integrated circuit designer in addressing the timing problems in an integrated circuit design.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
The preferred embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:
FIG. 1 is a block diagram of a computer apparatus in accordance with the preferred embodiments;
FIG. 2 is a block diagram of a first sample circuit in an integrated circuit design;
FIG. 3 is a block diagram of a second sample circuit in an integrated circuit design;
FIG. 4 is a flow diagram of a prior art method for adjusting slack in an integrated circuit design;
FIG. 5 is a flow diagram of a method in accordance with the preferred embodiments for adjusting slack in an integrated circuit design;
FIG. 6 is a flow diagram of a prior art method showing details of method 400 in FIG. 4;
FIG. 7 is a flow diagram of a method in accordance with the preferred embodiments showing details of method 500 in FIG. 5; and
FIG. 8 is a flow diagram showing one suitable implementation of step 730 of FIG. 7 in accordance with the preferred embodiments.
BEST MODE FOR CARRYING OUT THE
INVENTION
1.0 Overview
The present invention relates to static timing analysis of an integrated circuit design. For those not familiar with this subject, this Overview section will provide background information that will help to understand the present invention.
IBM EinsTimer
IBM developed a static timing tool known as EinsTimer. EinsTimer is used to automatically analyze the timing of an integrated circuit design at each node in the design. One specific analysis that EinsTimer performs is known as Linear Combination of Delays (LCD) analysis. LCD analysis allows modeling different amounts of delay in a set of logic blocks to generate worst-case timing scenarios. EinsTimer includes a feature known as Common Path Pessimism Removal (CPPR) that allows the tool to analyze the path for a clock test signal and a data launch signal and determine when both the clock test signal and data launch signal pass through a common block, and to give credit for the penalty imposed in the common blocks. EinsTimer's CPPR only gives credit when the clock test and data launch signal have the same edge when passing through those common blocks.
3
When the clock test and data launch signals have opposite edges, EinsTimer does not improve the pessimistic timing assumptions. As a result, EinsTimer may identify several timing problems that are not actually problems because it does not recognize the common path these signals pass 5 through. An example will help illustrate.
FIGS. 2 and 3 show sample circuits that could be implemented in an integrated circuit design. The circuits are made up of logic blocks. Thus, circuit 200 in FIG. 2 is made of logic blocks LB1-LB5. Circuit 300 in FIG. 3 is made up of 10 logic blocks LB10-LB14. The arrows at the input of LB4 and LB5 in FIG. 2 indicate the direction of the signal that latches the data. Thus, LB4 latches the data on the rising edge of the input, as shown by the up arrow on its input. LB5, in contrast, latches the data on the falling edge of the 15 input, as shown by the down arrow on its input.
Circuits 200 and 300 are identical except that LB5 latches data on the falling edge of the clock test signal while LB14 latches data on the rising edge of the clock test signal. This difference is significant, as shown below. 20
Static Timing Analysis Using EinsTimer
A prior art method 400 in FIG. 4 shows some of the steps a static timing tool, such as EinsTimer, performs static 25 timing analysis on an integrated circuit design. EinsTimer generates slack computations in the integrated circuit design (step 410). The slack numbers are then adjusted for circuits where the data launch and clock test are the same edge (step 420). Prior art method 400 thus improves the pessimistic 30 assumptions for circuit 300 in FIG. 3, because the clock test and data launch are the same rising edge. However, prior art method 400 does not improve the same pessimistic assumptions for circuit 200 in FIG. 2, because the data launch and clock test edge on LB5 occur on opposite edges. As a result, 35 the slack computation for circuits that have data launch and clock test on opposite edges is excessively pessimistic using EinsTimer.
One sample implementation of method 400 in FIG. 4 is shown in FIG. 6. First, two input pins on a logic block are 40 selected for a setup test (step 610). The clock arrival time using the fastest delay in the clock path is computed (step 620). The data arrival time using the slowest delay in the data path is then computed (step 630). The slack is computed as the difference between the earliest clock arrival time and 45 the latest data arrival time (step 640). We see from FIG. 6 that steps 610, 620, 630 and 640 implement step 410 of FIG. 4. If the clock test and data launch clock occur on the same edge of the clock (step 650=YES), the timing tool then determines a common path for clock and data (step 660). 50 The difference between the fast and slow delay times in the common path is then computed (step 670). The slack computed in step 640 is then given credit for the difference between the fast and slow delay times computed in step 670. We see from FIG. 6 that steps 660, 670, and 680 implement 55 step 420 in FIG. 4. A simple example will illustrate the details of method 400 shown in FIG. 6.
Referring to FIG. 2, we assume that the data and clock pins of LB5 are selected in step 610. The earliest arrival in the clock path computed in step 620 is 2+2+2=6. The latest 60 arrival in the data path computed in step 630 is 4+4+4+2=14. The slack computed in step 630 is the difference between the two, 6-14=-8. The negative number on the slack indicates a timing problem, because the clock can conceivably occur under best-case timing assumptions when the data is not yet 65 present under worst-case timing assumptions. Note, however, that assuming best-case timing for clock and worst
4
case timing for data in the circuit 200 in FIG. 2 is not reasonable, because both clock and data pass through common blocks LB1, LB2 and LB3. It is physically impossible for a logic block to provide best-case timing for one signal and worst-case timing for a different signal. For this reason, EinsTimer allows correcting the slack for signals that are based on the same edge.
Referring again to FIG. 6, the clock test and data launch signals on LB5 occur on opposite edges (step 650=NO). As a result, method 400 is done, and the pessimistic assumptions for slack remain unaltered. For the circuit in FIG. 3, the slack is computed in step 640 to be -8 using the same computation as for FIG. 2. The difference is that the clock test and data launch on LB14 both occur on the same edge (step 650). As a result, the timing tool may determine the common path for the clock and data (step 660). Incircuit300 in FIG. 3, the common path for clock test and data launch are blocks LB10, LB11 and LB12. The difference between the slow delay time in the common path (12) and the fast delay time in the common path (6) is then computed, with a result of 6 for this specific example in FIG. 3. The slack is then credited with the difference in step 680. Corrected slack=8+6=-2. We see from this simple example that the prior art method 400 improves the pessimistic timing assumptions for slack when both clock and data go through common blocks preceding the logic block on which the setup or hold test is being performed, but only for blocks that have data and clock occurring on the same edge, as shown in FIG. 3. The pessimistic timing assumptions for the circuit 200 in FIG. 2 remain uncorrected in the prior art because the clock test and data launch occur on different edges.
2.0 Description of Preferred Embodiments
The preferred embodiments improve known static timing tools such as EinsTimer by providing a method for adjusting the slack values for logic blocks where clock test and data launch occur on opposite edges to improve the pessimistic assumptions made during LCD analysis. Using the method of the preferred embodiments, a large number of timing errors may be eliminated with minimal input from the user.
Referring to FIG. 1, a computer system 100 is an enhanced IBM eServer iSeries computer system, and represents one suitable type of computer system in accordance with the preferred embodiments. Those skilled in the art will appreciate that the mechanisms and apparatus of the present invention apply equally to any computer system. As shown in FIG. 1, computer system 100 comprises one or more processors 110 connected to a main memory 120, a mass storage interface 130, a display interface 140, and a network interface 150. These system components are interconnected through the use of a system bus 160. Mass storage interface 130 is used to connect mass storage devices (such as a direct access storage device 155) to computer system 100. One specific type of direct access storage device is a CD RW drive, which may read data from a CD RW 195.
Main memory 120 contains data 121, an operating system 122, a static timing tool 123, a timing analysis mechanism 125, and an integrated circuit design 126. Data 121 is any data that may be read or written by any processor 110 or any other device that may access the main memory 120. Operating system 122 is a multitasking operating system, such as OS/400, AIX, or Linux; however, those skilled in the art will appreciate that the spirit and scope of the present invention is not limited to any one operating system. Any suitable operating system may be used. Operating system 122 is a sophisticated program that contains low-level code to manage the resources of computer system 100. Some of these
|
