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SYSTEM FOR TRANSFERRING FIRST AND
SECOND RING INFORMATION FROM PROGRAM STATUS WORD REGISTER AND
STORE BUFFER 5
this is a continuation of co-pending application Ser. No. 07/477,549 filed on Feb. 9, 1990, now abandoned.
BACKGROUND OF THE INVENTION ,0
1. Field of the Invention
The present invention generally relates to a microprocessor having a store buffer, and more particularly to a microprocessor in which data is written into an external memory through a store buffer independently IS of another instruction process.
2. Description of the Related Art
Recently, there has been considerable activity in the development of a microprocessor having a built-in cache and/or a store buffer, which is provided for re- 20 ducing the time it takes to access an external memory. Generally, such a microprocessor uses ring information for protecting the contents of the external memory from being damaged. Ring information is provided for each area of the external memory. For example, ring infor- 25 mation defines four different levels of "0', T, '2' and '3', in which ring level '0' is the highest. Ring information is used for discriminating a privileged level of an operating system against a non-privileged level thereof or preventing the contents of the external memory from 30 being mistakenly accessed by a task in a multi-task processing. Ring information on a program which is being processed is represented in a program status word (PS W). For example, when an area of the external memory is accessed by a program (instruction), ring informa- 35 tion on that area is compared with the current ring information described in the program status word. For example, when the area to be accessed has ring level '2' and the current ring information represents ring level '2', the access to the area is inhibited. 40
A microprocessor having a cache memory is known. Such a microprocessor has a mode in which data is written into a cache memory and an external memory at the same time. Generally, it takes a long time to write data into the external memory. It is noted that an in- 45 struction cycle in the microprocessor must be stopped until an instruction to write data into the external memory is completed. This deteriorates performance of the microprocessor.
From this viewpoint, a microprocessor having a store 50 buffer in addition to the cache memory has been proposed. In such a microprocessor, when data is written into the external memory, the data and a corresponding address of the external memory are written into the store buffer by an instruction to write data into the 55 external memory issued by a central processing unit (CPU). The execution of this instruction is completed when the address and data are written into the store buffer. Thus, the microprocessor can execute another instruction. On the other hand, when a bus provided 60 between the microprocessor and the external memory becomes available, data is read out from the store buffer and then written into the external memory independently of the execution of another instruction by the CPU. 65
When an error occurs while the data is being read out from the store buffer and written into the external memory, an exception processing request for processing
such an error takes place in asynchronism with a subsequent instruction which is generated after the instruction to write data into the external memory is completed. There is a possibility that a different exception processing request occurs when a subsequent instruction is being executed while the exception processing request for processing the above-mentioned error is being processed. From this point of view, it is necessary to consider priority between these different exception processing requests.
In the case where the microprocessor is designed so that the data write process using the store buffer is independent of another instruction, it is impossible to try to execute the instruction to write data into the external memory again from the beginning thereof when an error occurs while the data is being written into the external memory. This is because the instruction to write data into the external memory is completed when the data and associated address are written into the store buffer. For this reason, when an error is detected while data is being read out from the store buffer and transferred to the external memory, some information is saved in a predetermined area together with the program status word and an instruction address to which the process returns. For example, the abovementioned information to be saved includes an instruction address of the instruction to write data into the external memory, an operand address, operand data and control information on operand access. After the operating system removes the cause of error, data is read out from the store buffer and written into the external memory in accordance with the information to be saved. The control information on operand access includes an operand size and information whether or not it is necessary to translate a logical (virtual) address into a physical address.
Conventionally, ring information described in the program status word which is saved in the predetermined area, is used when trying to write data into the external memory again after an error occurs. The saved program status word relates to an address to which the process returns. Thus, the saved program status word has ring information indicating a ring level obtained when an instruction which is being processed in the store buffer at the time of detecting an error is completed. This ring level must be maintained until writing data into the external memory is retried. If the ring level is changed, some problems occur when writing data into the external memory is tried again. For example, a data write inhibit area of the external memory may be accessed in error so that the contents of the area are damaged.
For this reason, it is required to provide priority between the exception processes with a limitation. For example, an exception processing request other than an exception process request for processing an error occurring in the store buffer is accepted ahead of the latter exception process. However, when the former exception processing request is handled by the operating system, which generally has the highest ring level, the ring information described in the program status word is changed by information relating to the operating system. Thus the program status word to be saved by the exception process request for processing errors in the store buffer which occurs after the operating system runs, has information relating to the operating system. That is, in the program status word to be saved, no information is left which is obtained when reading out
data from the store buffer and writing the same into the external memory.
Alternatively, it is conceivable to accept the exception processing request for processing an error occurring in the store buffer ahead of other exception pro- 5 cessing requests. In this case, when an instruction to change ring information in the program status word is generated, the CPU cannot execute this instruction until the store buffer becomes available. For this reason, the microprocessor operates at a decreased processing 10 speed. In addition, when the above-mentioned instruction has a priority level higher than the exception processing request for processing an error occurring in the store buffer, this instruction is not allowed to be pro- j; cessed ahead of the exception processing process. Further, there is a problem. It is now assumed that an instruction has a basic length of two bytes and must have an instruction address having an even number without exception. If a branch instruction indicates an odd num- j0 ber branch address, an associated exception process request occurs. In this exception process, an address of the branch instruction and the inappropriate branch address must be saved. When the exception processing request for processing an error occurring in the store 25 buffer is accepted ahead of the exception processing request for processing the odd number branch address, information relating to the latter exception processing request is handled as information about the former exception processing request. As described above, a limi- 30 tation provided to priority between the different exception processing requests causes various problems.
SUMMARY OF THE INVENTION
It is a general object of the present invention to pro- 35 vide an improved microprocessor having a store buffer in which the aforementioned disadvantages are overcome.
A more specific object of the present invention is to provide a microprocessor capable of handling exception 40 (interruption) process requests in accordance with priority therebetween without any limitation.
The above-mentioned objects of the present invention are achieved by a microprocessor connectable to an external memory having a plurality of areas assigned *5 individual ring information for controlling access to said areas, said microprocessor comprising executing means for executing a program; and a register storing a program status word indicative of a status of said pro- ^ gram being executed by said executing means. The program status word includes ring information on said program being executed. A store buffer is operatively coupled to said executing means and is provided with write data to be written into said external memory and J5 a corresponding address when said executing means executes a write instruction, said store buffer having a specific area in which ring information on said write instruction is stored. The microprocessor further comprises control means, operatively coupled to said store $0 buffer and said external memory, for reading out said write data and address from said store buffer and writing the same into said external memory independently of executing said program by said executing means.
Further objects, features and advantages of the pres- 65 ent invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating an outline of a microprocessor according to a preferred embodiment of the present invention;
FIG. 2 is a block diagram illustrating a detailed configuration of the microprocessor according to the preferred embodiment of the present invention shown in FIG. 1;
FIG. 3 is a diagram illustrating a program status word;
FIG. 4 is a diagram illustrating the contents of each word stored in a store buffer shown in FIG. 2;
FIG. 5 is a diagram illustrating an operation sequence of the microprocessor shown in FIG. 2;
FIG. 6 is a diagram illustrating a format of information to be saved in an external memory shown in FIG. 1 when an exception occurs during a time when the memory is accessed; and
FIG. 7 is a diagram illustrating access information on an exception process which is requested when an error occurs while writing data from the store buffer into the externa] memory.
DESCRIPTION OF THE PREFERRED
FIG. 1 illustrates an outline of a microprocessor according to a preferred embodiment of the present invention. A microprocessor 100 is coupled to an external memory 200 through an external bus 300. The microprocessor 100 includes a central processing unit (CPU) 110, a cache memory 120, a store buffer 130 and a register 140 in a single semiconductor substrate. Data is written into the cache memory 120 and the external memory 200 at the same time. Data and associated information are written into the store buffer 130. The program status word (PSW) is registered in the register 140. As described previously, the program status word (PSW) includes the current ring information indicated by a reference *1 which indicates one of the predetermined ring levels. According to the present invention, ring information (indicated by a reference *2) on the write instruction to write data from the store buffer 130 into the external memory 200 is stored in the store buffer 130 independently of the register 140. When an error occurs while data is being read out from the store buffer 130 and written into the external memory 200, the ring information in the store buffer 130 is saved in the external memory 200. When the cause of the error is eliminated, the ring information saved in the external memory 200 is written into the store buffer 130. Thus, the CPU 110 is free to change the ring information *1 represented in the program status word (PSW) stored in the register 140 without any limitation in order to process a subsequent processing request, or an interruption or exception processing request resulting from a subsequent process. As a result, it is possible for the CPU 110 to execute a subsequent instruction without waiting for the completion of writing data read out the store buffer 130 into the external memory 200. Thus, the microprocessor 100 operates at increased speeds.
FIG. 2 illustrates a detailed configuration of the microprocessor 100 shown in FIG. 1. The CPU 110 shown in FIG. 1 includes an instruction decoder 17, a microprogram 19, an operation unit 20, a memory access control circuit 22 and an interruption/exception control circuit 23. The cache memory 120 shown in FIG. 1 corresponds to the combination of an instruction cache
13 and a data cache 29. The store buffer 130 shown in FIG. 1 corresponds to a register 26. The register 140 shown in FIG. 1 corresponds to a PSW register 25.
A program counter (PC) 10 has a counter which stores an address of a program being executed. The 5 program counter 10 has an instruction prefetch counter separately from the above-mentioned counter. A program address prefetched by the instruction prefetch counter built in the program counter 10 is supplied to a memory management unit (MMU) 11 and an instruc- 10 tion-side address translation circuit 12. The program address prefetched by the instruction prefetch counter is a logical address, which is converted into a physical address through the instruction-side address translation circuit 12. When the instruction cache 13 does not have IS an instruction associated with the physical address derived from the instruction-side address translation circuit 12, the memory management unit 11 accesses the external memory 200 (FIG. 1) through an internal bus 14, an external bus access controller 15 and the external 20 bus 16. The associated instruction read out from the instruction cache 13 is input to the instruction decoder 17, which decodes the received instruction and generates a corresponding micro-address.
The microprogram 19 receives a micro-address from 25 the instruction decoder 17 and controls the operation of the operation unit 20 and a register file 21 on the basis of the received micro-address. The microprogram 19 has a micro-processing routine to be activated when executing an exception process. The micro-processing routine 30 controls a saving process for transferring the internal status of the microprocessor to the external memory 200 when executing an exception process and a readout process for reading out a specific program status word and a specific program counter value from the external 35 memory 200. The memory access control circuit 22 controls an access request, the direction and size of the access requested. The micro-processing routine associated with the exception process is designated by the micro-address supplied from the interruption/exception 40 control circuit 23. The interruption/exception control circuit 23 is supplied with an external interruption request through a terminal 24, an exception processing request from the instruction decoder 17 to be generated when an unspecified instruction is detected, an excep- 45 tion processing request from the memory management unit 11, such as an address translation exception request or a bus access exception request, and an exception processing request from the operation unit 20, such as a zero-divide exception request. Then the interruption- 50 /exception control circuit 23 makes a decision on priority between the exception processing requests, and generates a micro-address relating to a selected one of the exception processing requests.
The PSW register 25 relates to a program which is 55 being executed, and has a format shown in FIG. 3. The . PSW register 25 has ring information (RING) 30, an address translation control mode (AT) 31, an interruption mask (IMASK) 32, and condition flags (CONDITION FLAGS) 33. The ring information 30 defines a 60 ring level of the program being executed by which the right to access the external memory 200 is controlled. The ring information is supplied to the memory management unit 11. The address translation control mode 31 indicates whether or not the address translation from 65 a logical address to a corresponding physical address should be executed. The interruption mask 32 indicates an interruption allowance level. The condition flags 33
are generated from the result of operation by the operation unit 20.
The store buffer 26 built in the memory management unit 11 is supplied with access information from the memory access control circuit 22 and the PSW register 25 through a terminal 27. The store buffer 26 is connected to the operation unit 20 through an operand address bus 71, and is connected to the operation unit 20, the register file 21, the program counter 10, the PSW register 25 and the data cache 29 through a data bus 72.
Each word having a multi-word structure stored in the store buffer 26 has a format shown in FIG. 4. Each word includes ring information (ACCRING) 40, a physical address code (PA) 41, a read/write code (RW) indicating the direction in which data is written or read out, an operand size 42, operand addresses 43 and 44, and write data 45. The ring information 40 relates to ring information at the time of accessing. The physical address code 41 indicates that there is no need for executing the address translation. The read/write code (RW) indicates the direction of data read/write. The operand address 43 is a logical address, and the operand address 44 is a physical address.
Referring to FIG. 5, there is shown a move instruction (MOV) having address #A to move data in a register RO (not shown) in the register file 21 to the external memory 200. The data in the register R0 is subjected to a data check procedure executed by the operation unit 20, which generates condition flags. Then the data in the register RO is stored in the write data area 45 of the store buffer 26 (FIG. 4). At this time, the current ring information in the PSW register 25 is written into the ring information area 40, and the physical address code (PA) 41, the code indicating the direction of read/write (RW) 42 and the operand size 42 are written into the corresponding areas in the store buffer 26. The move instruction (MOV) is a non-privileged instruction, which has a ring level of '3' when four different ring levels "0', T, '2' and '3' are provided.
When the aforementioned information is written into the store buffer 26, the memory management unit 11 activates a write processing sequence. When the address translation is requested, a physical address corresponding to logical address @MEM1 of the move instruction is calculated by the data-side address translation circuit 28. Then the obtained physical address makes a write bus cycle active. The program counter 10 determines that the execution of the move instruction is completed when the aforementioned information is written into the store buffer 26. Then the program counter 10 designates the address of a next instruction so that a microprogram of the next instruction is executed.
As shown in FIG. 5, a branch instruction (BRA) having address #6 is executed and a branch address @ADRS2 is calculated by the operation unit 20. It is assumed that the branch address @ADRS2 must be an even address, nevertheless it is an odd address. In this case, the operation unit 20 generates an exception processing request associated with the occurrence of an inappropriate address branch, and supplies the same to the interruption/exception control circuit 23. When the exception processing request from the operation unit 20 is accepted by the interruption/exception control circuit 23 and then transferred to the microprogram 19, the microprogram 19 executes an exception accepting process by which the program status word (PSW) obtained