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ADDRESSING AN INTEGRATED CIRCUIT mat and serially in rapid sequence as the counter ad
READ-ONLY MEMORY vances.
The present invention relates to a new, high access Word addressing in memory concurs with loading a speed, high cycle time data output rate, large scale inte- particular count number into the counter, to determine grated memory read-out circuit. 5 the beginning of byte string extraction. By external
The purpose of the invention is to provide an inte- control, read-out can be stopped before the last one of grated circuit chip from which stored data can be ex- the bytes in the sequence of extraction has been readtracted at high speed in a serial parallel operation. The out. This way, the length of a byte string to be extracted invention particularly relates to read-only memory of from one word location and by one addressing step is the MOS-variety with insulated gate type active ele- 10 varied.
ments (FET's). As the circuit is preferably constructed as an MOS
Read-only memories find utility in various fields of chip, the accessing operation is initiated, and in parts application. Among them is storage of micro-programs preceded, by a set up operation that includes preor code conversion for immediate control of composite charging all of the decoders, all of the addressing inputs character display in an "8" or a starburst or an even 15 for the memory, and all of the data extraction columns more elaborate pattern. In these and other cases rela- thereof as leading to the selection inputs. Sequentially, tive large amounts of data bits are to be made available, pre-charging is released and discharge takes place in all preferably in a particular format and in a short period but one of the decoder circuits as selected by the adof time. The integrated circuit chip constructed in ac- dress code. Thereafter, the pre-charge of the data lines cordance with the invention is designed to render the 20 is released, and, depending on the content of the adbits of a group (byte) available in parallel and several dressed word location, some of the data columns regroups or bytes are presented in sequence (byte string) mains charged others are discharged. The charged ones in response to a single addressing operation. Moreover, remain charged throughout the byte extraction sethe inventive design permits extraction of variable quence.
length byte strings, also in response to a single address- 25 A word read-out operation is internally terminated ing operation. The integrated circuit chip has a particu- through count completion or by selecting one of the lar layout that can be divided into memory cells proper bytes as a control byte of particular format that can be and controls. Upon making the chips, the masks are recognized as no-data. For example, it may be an alluniform as to the controls, also as to the general layout zero-bit byte to hich a particular decoder responds. In and arrangement of the cells, but differ as to the logical 30 either case, the circuit is latched to a reset condition content of the cells. Two such chips differing only in that is dynamically maintained upon continuation of this respect and addressed concurrently, but operated the clock. This way, the read-only memory can be by an external two phase clock in phase opposition can made randomly accessible as to individual bytes due to thereby be operated to present their outputs alter- byte addressing by counter presetting and selecting the nately, i.e., interleaved or interdigitized, so that twice ^5 next byte to be an all-zero byte.
the amount of data are made available in the same for- The initial set-up breaks the latch and sets up also the mat, i.e., as multi-bit bytes, and in the same period of counter to the present initial count number. As already time as far as presentation of all byte strings of the stated, read-out can also be terminated by an externally memory word location, having the same address in developed signal. Two such chips can be operated in both chips, is concerned. ^ parallel as to word address and byte count preset, also
In essence, the memory is a three dimensional mem- as to output. This way, the content of each word locaory projected into the two dimensions of an LC-chip. tion is doubled as to bits and number of bytes. The The three dimensions are: bit positions; word locations; number of bits per bytes is not changed, if an external byte numbers. However, byte number and bit position two phase clock is applied in the reverse to the two are collapsed into a single dimension, so that the data ^5 chips to cause them to operate interleaved for alternate are organized in a plane in which one dimension differ- outputting and, in effect, doubling of the data rate, entiates among addressable word location and the or- While the specification concludes with claims particthogonal direction has bit positions on a repetitive ularly pointing out and distinctly claiming the subject bases, the repetition defining the byte number. go matter which is regarded as the invention, it is believed
The inventive read-only memory has the following that the invention, the objects and features of the infeatures. Word address bits, i.e., an address word is ap- vention and further objects, features and advantages plied from the exterior to the circuit. A plural byte, sin- thereof will be better understood from the following gle word location is accessed through a decoder re- description taken in connection with the accompanying sponding to such an address word. The entire content 55 drawings in which:
of that location is rendered available on (internal) FIG. 1 is a block diagram of the read-only memory memory output lines, also called data extraction col- constructed in accordance with the preferred embodiumns. A presettable byte counter is provided for selec- ment of the invention;
tive outputting. The counter may be a regular counter FIG. 2 illustrates a logic diagram of a detail (bit-byte (binary, Johnson etc.) or a shift register. A selector 6Q selection);
gate or read select circuit has as many bit select circuits FIG. 3 illustrates schematically the operation of two as there are bits in a byte, each representing a bit posi- ROM-chips in parallel but interleaved through clock tion within a byte. Immediately upon addressing the phase reversal;
counter runs through its count states, and for each state FIG. 4 illustrates schematically the topological layout a different plurality of memory data extraction columns 65 of the ROM-chip as illustrated otherwise in the preced(corresponding to a different byte number) is coupled ing figures;
to the bit output circuits. These output circuits taken FIGS. 5a and 5b illustrate detailed circuit diagram of together provide the several bytes in parallel by bit for- representative examples of components and circuits as
used in the ROM-chip in question and interconnected includes a corresponding number of AND gates, orga
to illustrate the entire circuit layout of the block dia- nized in groups of nine each. This "AND-OR" arrange
gram shown in FIG. 1; and ment is schematically shown in FIG. 2. The outputs of
FIG. 6 illustrates an operational timing diagram. respective nine AND gates are OR'd together to pro
The circuit illustrated in FIG. 1 includes a plurality 5 vide one output that is applied to one input terminal of
of input terminals for receiving the various operational a buffer, having an output terminal. There are eight
signals from outside of the chip. Among them are the such OR gates corresponding to eight bits per byte and
location address signals A, to A5; external phase signals feeding eight buffers 40 having output terminals desig
tjil and <f>3 in alternating, spaced-apart sequence; the nated OUT-0, 2, ... 7.
setup signals $1T, <j>2T, E, all providing phase signals 10 The selection of the AND gates for each OR gate is that concur with the presentation addressing bits Ai under control of a select counter 50. The counter may etc. The set-up signals may have common leading edge be regular binary counter or a shift register with nine but should have sequential release. This sequential re- output lines C„ to C9, each line being fanned-out eight lease is important not only for timing commencement fold, to provide concurrent gating signals to eight AND of operation but for supplying sufficient power. Next, 15 gates of the select circuit 30. The counter signals prothere is the external (possibly asynchronous) disable vide gating for but eight out of seventy-two AND gates signal D to stop any read-out in progress. Addressing as only one out of nine counter outputs is true at a time, signal Bl, B2, B3, provide bit string length selection Thus, counter 50 controls coupling of the data extracand VDD (FIG. 5a) is the operating dc power supply tion columns b0 to b7l to buffer output lines OUT-0 to voltage. 20 OUT-7 in that eight data extraction columns are so Preceeding now to the circuit, the input address sig- coupled concurrently, and each buffer output is senate A, to A5 are applied to inverters 10 to form the re- quentially coupled to nine different data lines in proquired complements, and the signals A,, A1; A2, A2 etc. gression of the counter.
are next applied to a full decoder 15 having 25 = 32 Thus, for count state 0, column b0 is coupled to OUT
output lines a0 to a31. The inverters 10 (as well as in- 25 0, column bg is coupled to OUT-1, column bls is cou
verters 60, infra) are set up in response to signal E, the pled to OUT-2, etc., and column bS3 is coupled to OUT
decoders 15 are set up in response to signal <£1T. It can 7. For count state 1, column b^ is coupled to OUT-0,
be seen from the topologic scheme of FIG. 4, the out- column b10 to OUT-1 . . . column bM to OUT-7. For
put lines aa to a31 lead to plating runs or strips to consti- count state 2, column b2 is coupled to OUT-0, bu to
tute gate electrodes in FET's of a data matrix 20. 30 OUT-2, i>20 to OUT-3, etc., fc^ to OUT-7. After nine
The data matrix 20 on the IC-chip is comprised of an counter clock times, upon count state 8, column ba is
array arrangement of (for example) P-zones in an n- coupled to OUT-0, etc., b71 to OUT-7. Thus, the 72 bits
type substrate, extending in one direction of the matrix, of each word location of the memory are extracted
for example as columns thereof. This arrangement is from and called up in the data matrix in form of a byte
more fully shown in FIG. 4. Some of these runs of P- 35 string of nine bytes (or less as will be described), each
zones are permanently connected to ground; they are byte having, of course, eight bits presented in parallel
selected so that each P-zone run which is not grounded, on the buffer output. During this time, the entire partic
is flanked by but one run that is grounded. Two such ular word location remains gated on, and the bit and
P-zones define a data column. Intersections are defined byte extraction is carried out through the counter and
where the gate plating strips as matrix rows pass across 40 sequencer 50.
respective non-grounded P-zones. Such an intersection The second set of addressing signal Bl, B2, B3, is ap
defines an addressable memory location to the bit level plied to inverters 60 to form the complementary sig
or bit cell. If that area together with the closest, nals, and signals Bl, Bl, B2, etc., are decoded in a full
grounded P-zone is developed as a transistor (through decoder 65. The eight different outputs of this 23
thinning of the oxide layer on the chip), the location 45 decoder are coupled to the first eight (i.e., all except
defines a stored bit of value "one"; if the area is not de- the last) stages of counter 50, to determine the count
veloped as a transistor the location defines a bit of state at the begining of read-out operation. For extrac
value "zero." tion of the full length string of a word location, the
All non-(permanently)grounded P-zones define counter code is Bl =B2 = B3 =0, and the first counter memory extraction columns. There are, for example, state is established for the counter to begin the extrac72 such columns be to blu corresponding to 72 loca- tion sequencing with the first byte in the addressed tions to the bit level for one addressable location to the word location and as defined by the eight bits on colword level. Upon providing gating-addressing voltage umns b0, ba, etc. For a different, not all-zero bit combito one of the addressing lines a0 to a3U all transistors de- 55 nation Bl, B2, B3, counter 50 is set to a correspondveloped thereunder are rendered conductive, and the ingly different state from which to shift, and to adpotential of all columns b0 to b71 at that time is indica- vance, so that some of the bytes of the word location tive of the respective bits of that 72-bit word then read- are not called up and extracted (though available), out. A byte string counter 90 may be provided externally,
The 72 output or extraction columns of the ROM- 6Q subject to external control as to the length of the byte data matrix 20 are connected to a read select and bit string to be read, particularly in case read-out is to be merge circuit 30. The circuit 30 is comprised essen- terminated before the last one of the bytes within the tially of gates with ight output lines leading to eight out- call-up sequence has been read. That counter 90 may put buffers 40 from which output signals are extracted produce the termination signal D. Thus, upon addressexternally. The select circuit 30 extracts eight bits (one fi5 ing a word location, all eight data bytes of that location byte) in parallel out of the 72 bits as presented upon could be presented as a byte string in eight sequential addressing of a word location. The select circuit 30 has clock cycles. Numbering these bytes 0 to 7 with an these 72 data extraction columns b0 . . . bn as input and ninth byte being all zeros, these bytes are presented in
that sequence. In dependence upon the code Bl, B2, as last column of the other chip for termination. The B3, the byte call up sequence can actually begin with delayed operated chip provides reset latching in rebyte No. 1, or byte No. 2 etc. Upon selecting the timing sponse to counter control thereon. These points are of production of signal D, the read-out sequence can be mentioned here only summarily, they will become terminated before the eight's byte has been presented. 5 more apparent below and pursuant to the detailed deNote that all bytes are always read-out and set into col- scription of the circuit shown .in FIG. 5. umns b„ to b7, and the restriction of byte extraction is In FIG. 5, boxes with letters denote schematically the operative only as restriction as to which bytes are being lead-in electrodes and immediate input circuitry incalled upon by the counter 50. volved for receiving input signals as designated by these The inverters 10 and 60, decoders 65, the stages of 10 letters (A, E, D etc.) A circuit 80-1 produces phase counter 50 and latching circuit are all set, i.e., prepared clock <\>2 out of <j)l and tf>3, a circuit 80-2, similarly and pre-charged, by set-up signal E having longest du- constructed but connected to phases <j>l and <f>3 in the ration. The same holds true for a latching circuit 70. reverse, produces <jA. An inverter 81 produces E out of The circuit 70 is actually a decoder that responds to E (see portion Sb of FIG. 5).
one of three conditions which ever occurs earliest, to 15 The addressing input signals Al ... A5 pass through clamp the operational state of the circuit to an all-zero inverters such as 10-1 with signal E serving as gate concondition out of which it can only be raised by the tri- trol for one of two transistors 11 and 12 connected in plex of control inputs <f>lT, <j>2T and E. series. Transistors 11 and 12, when conductive, have
The reset latch condition may be established upon impedance ratio so that low voltage is passed as signal
decoding the last byte, if it has only "zeros" (or "ones," 20 Al = 0; for Al = 0 only one transistor is conductive
depending on definition). Latch condition decoder 70, and applies VDD (minus transistor threshold) as signal
as connected to the output lines of read selector 30, re- A„ = 1. There are similar inverters for the other ad
sponds and clamps the outputs thereof to zero. Addi- dressing signals, and collectively they constitute the in
tionally, the last shift state of counter 50 has the same verter circuitry 10. _
result, but only after outputting of the ninth byte has 25 The, altogether 10 signals A,, A,, A2 . . . etc., as they
been enabled. Finally, the latch circuit 70 responds to appear in any instant, are processed in decoders 15
the externally produced signal D that is in fact a read- such as decoder 15-0 for responding particularly to the
halt signal and may be produced, for examle, because address (Aj, A2 . . . A5) = (0,. . . , 0). There are thirty
the output circuit cannot accept any longer the data two such decoders, 15-0 through 15-31. Each decoder
supplied by the ROM, or because of intentional format 30 is constructed from five FET's, such as 16-1, 16-2, . .
and content restriction in the particular case as deter- ., 16-5 for decoder 10-0, and the respective five FET's
mined, for example, by the counter 90. are connected parallel. The five transistors of a de
The circuit is completed by the internal phase clock coder are connected to a plurality of five signal lines
80. External phase signals, called <j>l and </>3, are pro- selected Jrom the 10 lines that receive the signals A,,
cessed herein to produce interspaced clock pulses $2, 35 Al5 A2, A2 etc. A decoder, such as 15-0 responds if
$4, so that a four phase clock is available. A full cycle none of its five transistors is rendered conductive. Thus,
<j>2-, <j>3-, <f>4- has, for example, about 200 nano- the five transistors 16-1,... 16-5, receive the five sig
second period, each pulse, thus, having about 50 nsec. nals A1; A2, . . . A5, so that for A, = A2 = . . . = A5 =
duration. A first (dummy) cycle begins and covers 0 none of these transistors is rendered conductive. The
about the period ofE. At the trailing edge of E, <f>l of 40 other decoders receive different_signal combinations,
the first operating cycle occurs and the first byte is decoder 15-31 receives (A, . . . A5).
read-out, "first" to mean here as determined by the The interconnected source electrodes of the five
byte string begin code (Bl, B2, B3). FET's, pertaining to a decoder, are biased to negative
In case a chip is used with external clock <f>l and (f>3 potential by signal <£1T, while for <f>U = 0 ground po
reversed, such a chip operates at a 180° phase shift 4^ tential prevails on these source electrodes. Hence, all
(100 nsec.) as far as each byte read cycle is concerned. decoders are so biased by signal <f>lT. The drain elec
As bits are presented for each 100 nsec, bit presenta- trades of the five transistors of a decoder are connected
tion by a chip is on intermittent basis and two chips op- to a transistor such as 17 pertaining to the particular
erated in phase opposition, thus, provide bytes on an . decoder 15-0 and connecting biasing voltage VDD to
alternating basis. This mode of operation is used in the the interconnected drain electrodes upon and for the
circuit of FIG. 3. There are two substantially similar duration of <f>lT, controlling the gate potential of tran
chips No. 1 and No. 2, each constructed as schemati- sistor 17. The interconnected drain electrodes (as a P
cally shown in FIG. 1, but operated in phase opposition zone in the IC-chip) of the five decoder transistors
as defined; otherwise they receive the same addressing ^ 16-1 etc. lead to the gate plating a0 for addressing the
signals and are set up concurrently. As each chip pres- lowest address word location on and along that plating
ents its bytes (for a single addressed word) at a 5 Mhz in the data matrix. Gate plating a0 establishes a node on
rate, two chips operating interleaved together present the interconnected drain electrodes of the decoder
twice the number of bytes in the same time correspond- transistors and that node is charged on <£1T.
ing to a rate of 10 Mhz. As each chip presents eight ^ Theother31 decoders are similarly constructed, sim
bytes, two chips together present sixteen bytes within ilarly biased and have similar pre-charged nodes that
the same period of time. lead to and are established by the addressing lines a, to
The two chips differ slightly as to content of the a3l. Each line serves as gate plating strip for a 72 bit lo
ROM matrix (other than the expected difference from cations of the data matrix; all of these addressing lines
chip to chip). The chip operating delayed relative to fi5 are pre-charged as nodes.
the other one has a dummy column as a first column, As signal E has duration longer than signal <£1T, the
as for reasons of relative timing, that column cannot be d-c control of the ivnerters persists beyond the decoder
properly read. A latch-out-all-zero-column is provided pre-charge period to facilitate establishing of charge
and discharge conditions of the several capacitances as establishing the nodes. Upon addressing and after release of signal <j>lT, all but one of the nodes on lines a0 to a3t are discharged as all decoders but one have at least one FET conductive to permit node discharge through the now grounded line that provided <£1T during the precharge-set-up period and to which all decoder FET's have their source electrodes connected. The node and address line that is not discharged controls, in turn, discharge through transistors of the data matrix to which I now turn.
The data matrix includes addressing gate lines a0 . . . a31 as defining the rows of the matrix. The matrix columns are deonted 20-0, 20-1,... 20-71. They are established by and between pairs of runs of P-zones extending orthogonal to the rows. Each such pair of Pzones is crossed over by all 32 addressing lines and defines 32 bit cells, one bit position each for all 32 word locations. Each data column is established by two adjacent P-zones, one thereof serving as a data extraction column. There are 72 extraction columns, b0 to b7J. Take data column 20-0, it has data extraction column b0 as well as a second P-zone, denoted here 22-0.
The P-zone ba serves as a drain electrode and zone 22-0 as source electrode for transistors on the data column establishing a particular bit value. Any developed transistor in the data matrix and particularly in an intersection of an addressing line, and of a data column establishes a bit of particular value as stored in that intersection. Transistor 21 is, for example, connected with its gate to line a0 in representation of bit value 0 (or of a 1, the assignment is arbitrary) in the first bit position of the lowest address word location. Absence of a developed transistor in such an intersection establishes a stored bit of complementary value in that bit cell.
There must be one extraction column per data column, but the additional P-zones, such as 22-0, are provided in between respective two extraction columns, such as 20-0 and 20-1 and are, thus, shared by adjacent data columns. The columns 22-0 and others are biased by set-up signal <j>2T but are held to ground potential thereafter, to establish source electrode potential for the various transistors of the data matrix.
The data extraction columns b0... b71 are themselves nodes, and all of them are pre-charged on set-up time, concurrently and also by signal <j>2T. For this, each data column is connected to voltage source VDD via the drain-to-source path of a transistor, such as 23-0 as connected to column b0, transistor 23-1 as connected to zone or column fc, etc. The set-up signal <£2T controls the gates of these transistors 23-0 etc. Upon decay of set-up signal <£2T a data extraction column connected to a developed bit cell transistor that has its respective gate connected to the respectively addressed data matrix row and gate line, is discharged. A data extraction column which does not have a developed bit cell transistor at the intersection with the addressed data matrix row and gate line, remains charged.
In the illustrated example columns b0 and b70 (and possibly others) will be discharged upon addressing the word location of lowest address code (addressing gate line a0). The discharge of a data extraction column occurs after the non-addressed lines, (e.g., a3 ... a31) have been discharged, as set-up signal <j>2T persists beyond the duration of set-up signal <j>ff. In other words, all decoder nodes but one of the memory address gates (matrix rows) are discharged first, before the non
discharged data matrix row can take effect for controlling the gates of developed transistors along that row, and only thereafter, upon release of <f>2T, will data extraction columns discharge along which there are gat5 ed-on, developed and addressed bit cell transistors (such as 21).
The selective charge state of columns ba to b7l as resulting from addressing and selective discharge persists throughout the next operating phases during which the
10 content of the addressed word location, as now presented on the columns b0 to b71, or a portion thereof, is called up in sequential bytes. It should be noted that the address signals A,, etc.,_can be removed when the signal E turns false. E -» E, The particular gating opera
15 tion of the previously addressed matrix row is no longer needed. The discharged data columns will not recharge and the data columns that were not discharged are isolated and will remain charged. There will be some leakage discharge but that leakage is not noticeable for
20 many clock cycles. A minimum period for charge retention must extend over at least nine clock cycles for a 5 Mhz clock, that period is about 2 microseconds. Actually, the charges are retained for much longer periods so that there will be no problem.
25 As outlined above, and as will be justified below, bit cell transistors are not at all developed along columns bs, bl7 . . . b7X so that these columns are never discharged. This is true only for a chip that does not operate with a companion chip of the interleaved mode,
3° or if there is a companion chip, the latter is the one that lags by half a clock cycle. In that case, the latter chip has no developed transistors along columns ba, b9, . . .
The data output columns b0 to b7i lead to the read se
35 lect circuit 30. As stated, there are eight bit select circuits 30-0,.. . 30-7 commensurate with the eight bits of a byte to be read-out concurrently, i.e., in parallel. Of these eight bit select circuits, one thereof, 30-0, is developed in detail. The purpose of this bit select cir
40 cuit 30-0 is to sequentially select the nine bits on columns b0 to fo8 (or a lesser number) to serve as lowest order bits in nine (or less) sequential bytes as extracted from the entire content of an addressed word location. Thus, circuit 30-0 has the nine columns ba to bg as in
45 puts. A similarly constructed circuit 30-7 has columns bes to b71 as inputs, etc., for selection of the respective eighth order bit in each of the bytes of the byte string to be extracted.
50 Each one of the columns bQ to bH connects to the respective gate of a transistor, 31-0 to 31-8. These transistors have interconnected drain electrodes and are connected therewith to phase clock line <f>t. Each transistor has its respective source electrode connected to
g5 the drain-to-source path of a counter controlled transistor; in particular, a transistor 32-0 is gated on by the count state signal in counter output line CO, a transistor 32-1 responds to CI, etc., transistor 32-8 to the count state signal in line C8,
Each pair of series connected transistors, such as 31-0, 32-0 or 31-1, 32-0, etc., constitutes an "AND" gate of the particular merge section 30-0 (compare with FIG, 2). The connection in parallel of these nine transistor pairs constitutes the OR-connection. The in
65 terconnected source electrodes of transistors 32 are connected to a node 35-0 via a transistor 33. Node 35-0 is charged by and during each phase #1 as controlling a transistor 34. Phase signal 4>2 is the data ma