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GOU) FILM ETCH© VIA PHOTO RESIST
RELEASE «»x «\ 1<*\
FLEXIBLE TESTER SURFACE FOR TESTING
This application is a division of application Ser. No. 5 07/194,596, filed May 16, 1988, issued May 15, 1990 as U.S. Pat. No. 4,924,589.
BACKGROUND OF THE INVENTION
1. Field of the Invention 10 This invention relates to a method of making and
testing integrated circuits, and a device used to perform such testing.
2. Description of the Prior Art
Integrated circuits (ICs) comprise active and passive 15 elements such as transistors, diodes, resistors, and capacitors, that are interconnected in a predetermined pattern to perform desired functions. The interconnections are effectuated by means of metallization layers and vias. A "via" is a hole through an insulation layer in 20 which conductor material is located to electrically interconnect one conductive layer to another or to an active or passive region in the underlying semiconductor substrate. Present day technology generally employs two metallization layers that are superimposed 25 over the semiconductor wafer structure. Integrated circuits and assemblies have become more complex with time and in a logic circuit, the number of integrated circuit logic units (ICLUs) and interconnects on a given size die have been substantially increased re- 30 fleeting improved semiconductor processing technology. An ICLU can be a device (such as a transistor), a gate (several transistors) or as many as 25 or more transistors and other devices.
Standard processing to make logic structures (e.g., 35 gate arrays) includes first fabricating as many as half a million transistors comprising a quarter of a million gates per die. Each semiconductor wafer (typically silicon but sometimes of other material such as gallium arsenide) includes many die, for example, several hun- 40 dred. In one type of gate array, for example, the transistors are arrayed in rows and columns on each die, and each transistor is provided with conductive contact points (typically metal but sometimes formed of other conductive material such as polycrystalline silicon), 45 also arrayed in rows and columns. As is well known in the art, these conductive contact points have a typical center-to-center spacing of about 6 to 15 microns (jam).
In the prior art, the next step is to use fixed masks to fabricate the conductive layers (sometimes called "met- SO allization layers"), to connect together the individual gate-array devices. Typically two or sometimes three metallization layers are used.
After this, the completed die is tested. If any of the devices on the die are defective, that die will fail an 55 exhaustive test and be scrapped. Therefore, the more transistors per die the lower the manufacturing yield. In some cases redundant sections of a circuit are provided that can be substituted for defective sections of a circuit by fuses after metallization. Typically such redundant 60 sections can be 5% to 10% of the total circuit.
SUMMARY OF THE INVENTION
An object of this invention is to provide an improved test procedure for integrated circuits to increase pro- 65 duction yields, by testing a circuit at the ICLU level (hereinafter called "fine grain testing"), compared to conventional testing at the functional IC or die level.
Another object is to permit the fabrication of very large integrated circuits, in terms of number of ICLUs or devices per circuit.
The present invention improves on prior art by testing each ICLU prior to metallization. Redundant ICLUs are provided on the die to substitute for those found to have defects. Then the metallization layers are fabricated so as to exclude defective ICLUs and substitute good ones from the redundant group and render the circuit operable. The present invention uses a fine grain testing approach, by testing at a low level of complexity.
One key to the present invention is a specially fabricated flexible test means made of flexible silicon dioxide in one embodiment and including multi-layer metal interconnected and microscopic test points. The flexible tester means includes a tester surface, connected to test equipment, that permits testing of each device. Then by CAD (computer aided design) means, each die is metallized and the metal layer is patterned by suitable means, such as E-beam processing, to fabricate discretionary metallization interconnect layers of individual gate array devices.
The tester surface is formed on a standard silicon wafer typically by means of a low stress chemical vapor deposition process. The tester surface includes its own metallization layers. On one side of the tester surface are thousands of probe points to contact the contact points on the wafer under test. The tester surface is a special flexible form of silicon dioxide which can be pressed flexibly against the wafer under test to achieve good electrical contact.
By eliminating defects at the device level, process yield is vastly increased—for example to about 90% regardless of die size, in contrast to much lower yields using prior art technology. The present invention also allows successful fabrication of very large die compared to conventional technology.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 shows a section of a gate array wafer and the device contacts.
FIGS. 2-3 show a top and side view of part of the tester surface.
FIGS 4(a) and 4(6) show the test procedure.
FIG. 5 shows the fluid pressure test assembly.
FIG. 6 shows an exploded view of the wafer and tester surface.
FIGS. 7-12 show the steps to fabricate the tester surface.
FIGS. 13-15 show the steps to fabricate another embodiment of the tester surface.
FIG. 16 shows how nine die can form one super die.
Each reference numeral when used in more than one Figure refers to the same structure.
As stated above, the prior art fabricates a plurality of transistors on a die, interconnects the transistors to form desired logic, tests the entire die, and scraps the die if the logic doesn't work. In the present invention, after fabricating the transistors exactly as before, the transistors or ICLUs are tested individually. Then the interconnect scheme is modified, if necessary, by CAD means (of well known design) to bypass defective transistors or ICLUs and substitute, logically speaking, replacement ICLUs. Then the metallization layers are deposited, and patterned in accordance with the modified interconnect scheme typically by E-beam (Electron-beam) lithography, instead of the masking process of the usual conventional technology. Thus each die has its own unique interconnect scheme, even though each die is to carry out the same function as the other die. S
The present invention in one embodiment begins with a gate array conventionally fabricated on a silicon or GaAs wafer. The gate array transistors are arrayed in columns and rows on the wafer surface 1, and the active regions of each transistor are provided with contact 10 points such as 2-1 to 2-32 which are in columns and rows also as shown in FIG. 1 (not all contact points are numbered). Redundant (or extra) devices are designed into each column, with a redundancy factor dependent on the expected yield of the individual transistors or IS ICLUs being tested.
The surface of the wafer 1 is optionally pianarized with a cured layer of polymide 0.8 to 1.5 micron thick if the step heights between contact points are greater than 0.S microns. (The contact points 2-1 to 2-32 are 20 masked from the polymide layer, to create a via over each contact point free of polymide, and metal is deposited to fill the via.)
The fabricated (but not metallized) wafer 1 is now ready for testing. In the described embodiment, only 25 one column of transistors on each die is tested at a time, although testing more than one column per step is possible. For a die of typical complexity this requires making contact with all of the perhaps 10,000 or so contact points such as 2-1 to 2-4 in one column simultaneously, 30 and then stepping across all 100 or 200 or more columns in each die, to totally test each die in step-and-repeat fashion. Each contact point such as 2-1 is small—usually 4x4 microns. Each wafer contains a plurality of die, the exact number depending on the size of the wafer but 33 typically being in the hundreds. It is also therefore possible to test more than one column at once to perform testing on the ICLU's.
The flexible tester of this invention includes a tester surface 10 (described in detail below) as seen in FIG. 2 40 which includes a series of tester surface contact points including 15-1, 15-2 (which are arranged to contact on a one-to-one basis the corresponding contact points in a column on the die under test) and a complete wiring interconnection, including a testing array which in- 45 eludes contacts 16-1, 16-2 and 16-3 and interconnect pathways 17-1, 17-2 and 17-3 as seen in FIG. 3, at various levels 22, 23, 24, in the tester surface. The tester array which includes contacts 16-1, 16-2 and 16-3 connects to a conventional tester signal processor as shown 50 in FIG. 4a having line driver logic circuits for accessing serially or in parallel the devices under test. The driver logic signals are programmed separately in a well known manner and are multiplexed between testing array contacts 16, providing programmable input/out- 55 put means for supplying diagnostic signals to the transistors or ICLUs under test. Therefore, all the wafer contact points in one column can be accessed in one physical contact step of the transistors or devices to be tested. 60
The wafer 1 under test and the tester surface 10 are disposed on a support 26, as shown schematically in FIG. 4(a), for test purposes, to electrically connect the contact points on the tester surface 10 and corresponding contact points on the wafer 1. FIG. 4(6) shows the 65 test procedure in process-flow format. A fluid well or bladder (not shown) is used to exert an uniform pressure over the flexible tester surface 10 (FIG. 4(a)) in order to
conform it to the surface of the wafer 1 under test and to ensure that the numerous corresponding contact points on the tester surface 10 and the wafer 1 come together and make firm electrical contact. This is possible due to the fact that the surface of the wafer 1 under test typically has a controlled total runout flatness within 6 to 10 microns across its complete surface. Secondly, the tester surface 10 is less than IS microns thick and typically l.S microns thick and of a very flexible material, such as low stress silicon dioxide. Thirdly, the metal contact points are the highest raised surface features on either the tester surface 10 or the surface of the wafer 1 under test, and are of a controlled uniform height typically between 2 and 6 microns.
The wafer 1 under test as shown in FIG. 4(a) is mounted on an x-y motion table (not shown). Movement of the table in the x-y directions positions the wafer for test by alignment of the contact points such as 15-1 and 15-2 of the test surface 10 (FIG. 2) with the corresponding device contact points such as 2-1 and 2-2 of the wafer 1.
During the test procedure as shown in FIG. 4(a), the wafer 1 under test is retained by suction in a substantially planar fixed position, by means of the support 26 illustrated in FIG. 4(a) and in FIG. 5. Use of suction to hold a wafer in place is well-known. Tester surface 10 is mounted on a support ring 36 (as described below) to provide mechanical support and electrical connections, as shown in FIG. 5. The tester surface 10 is urged uniformly toward the wafer 1 under test by a fluid well or bladder 38 immediately behind tester surface 10. A solenoid (not shown) is provided for macro control of the pressure exerted by the fluid in the fluid well 38 on tester surface 10. The depth of fluid well 38 is less than 100 mils; this is the distance between the back of tester surface 10 and piezoelectric pressure cell 40.
Piezoelectric pressure cell 40 is a layer of material about five-hundredths of an inch (one millimeter) thick that will expand about one-half micron when voltage is applied to the piezoelectric material. The applied pressure on the back of the tester surface 10 is only a few grams per square centimeter. Piezoelectric pressure cell 40 provides the last increment of pressure on the fluid and in turn on the back of tester surface 10 to achieve good electrical contact between the contact points such as 15-1 and 15-2 on tester surface 10 and the contact points such as 2-1 and 2-2 on wafer 1. The fluid is provided to the assembly through fluid port 46 which is connected to a fluid reservoir (not shown). The support ring 36 includes computer cabling attachment sites 48 and multiplexer circuits 50. The support ring structure is described in more detail below.
As described above, mechanical positioners (i.e., x-y table aligners and conventional mechanical vertical positioners, not shown) bring the wafer 1 to within a few mils of the tester surface 10 and make a first approximation of the alignment of contact points through a conventional optical aligner (not shown). The optical alignment is performed in a manner similar to that used by present semiconductor mask aligners, by using alignment patterns in predetermined positions on both the wafer 1 being tested and the tester surface 10. Only the pressure of the fluid moves the tester surface 10 the one or two mil distance separating the tester surface 10 and the wafer 1 to be tested in order to gain physical contact. FIG. 6 illustrates in an exploded view wafer 1 and tester surface 10 being moved by fluid pressure from fluid well 38 just before wafer contact points such