same time. Then, data in latch circuits 441 to 444 are NONVOLATILE SEMICONDUCTOR MEMORY supplied to load transistors 471 to 474 via inverters 461 HAVING PAGE MODE PROGRAMMING to 464 and are thus written into the four-bit memory
FUNCTION cells at the same time. Next, in the verify mode in which
5 signal PGM is set at a high level and signals CE and OE BACKGROUND OF THE INVENTION are both set at a low level> the pr0grammed data is read
1. Field of the Invention out.
This invention relates to a nonvolatile semiconductor In the programming operation of the normal mode, memory, and more particularly to a circuit for latching one of normal mode programming control transistors program data and at the same time programming data. 10 481 to 484 is selected according to address input bits AO
2. Description of the Related Art and Al, and input data is programmed via the selected It has been required to shorten the programming time load transistor.
in nonvolatile semiconductor memories such as ultravi- As described above, three signals PGM, CE and OE olet erasable programmable read only memories can be variously combined to selectively set various (EPROMs) as the memory bit density increases. There- 15 modes of operations of the normal mode programming, fore, the memories tend to be formed so as to have the page m0(ie programming, programming inhibition, verpage mode programming function of latching program ify> ... of page mode programming data and the data of several bytes and then simultaneously program- Jjj^
ming the data into a plurality of memory cells. In gen- In a case where si , is omitted and om the eral, it is necessary to effect both the page mode pro- 20 ... ^ ^ Ce OE are used, the circuit of gramming operation and normal mode programmmg plG 4 ... ^ ^ fc ... solye ^ w operation. Conventionally, the page mode and normal ., .„ ^. , , ., , TM_ r. . ,'
male are selectively specified by a combination of input the f°llowmS cTM ^ considered That is, data
logic levels of four external input terminals (program- nmy be latched in a short low-level penod(Tl) of signal ming power supply voltage, PGM input terminal, chip 25 CE, and the latched data may be programmed or writenable CE terminal and output enable OE input termi- ten m a longjow-level penod T2) of CE signal. In this nal) case, signal OE is kept at a high level m the page mode
Such a prior art is disclosed in the following docu- programming operation, and is set to a low level for ments: ea°h data output. Further, in this case, when it is deter
Takaaki Hagiwara, et al. 30 mined by use of a timer that a preset period of time
SESSION XIII: NONVOLATILE MEMORIES (long low-level period of signal CE) has elapsed after "Page Mode Programming 1 Mb CMOS EPROM", signal CE was set to a low level in the normal mode 1985 IEEE International Solid-State Circuits Confer programming operation, data is started to be proence, ISSCC 85/THURSDAY, FEB. 14, 1985, pp. grammed.
174-175 35 However, time loss occurs before the beginning of
The entire contents disclosed in the above documents programming in the normal mode programming operaare incorporated into this specification. tion effected by use of the timer, and necessary proPart of the conventional EPROM is shown in FIG. 4 gramming time becomes longer. In other words, when and the operation timings thereof is shown in FIG. 5. it is desired to control the page mode programming and Data input/output terminal 41 is commonly connected 40 normal mode programming operations according to to one end of data latch control transistors 431 to 434 of tw0 control signals, the programming time in the norfour bits via inverter circuit 42. The other ends of tran- mal programming operation will become longer, sistors 431 to 434 are respectively connected to input
terminals of latch circuits 441 to 444. The output termi- SUMMARY OF THE INVENTION
nals of latch circuits 441 to 444 are respectively con- 45 ^ object of this invention is to provide a nonnected to the gates of programmmg or bit lme load volatile semiconductor memory in which both the page transistors 471 to 474 for progranmung, vui page mode mode programming and normal mode programming programming control transistors 451 to 454 and inverter operations can be achieved according to two control circuits 461 to 464. Transistors 471 to 474 are respec- ^ for j a ^ enablfi sj ^ m ^ QUt.
tively connected to bit lmes BL1 to BL4 which are in 50 °. ,. , /7=«W\ J A J *
'... i * ii i4v-i • put enable signal (OE), and the data programmmg time
turn connected to a plurality of memory cells MC... via v , j t_ , x t.- j. ■ ;A
column selection transistors (not shown). Further, the ^ be reduced by latchm«
output terminal of inverter circuit 42 is connected to the the same time programming the data,
input terminals of inverter circuits 461 to 464 via normal The ^volatile semiconductor memory of this m
mode programming control transistors 481 to 484, re- 55 vention is constituted to latch or load the input data (Dl
spectively t0 D4) mto a data latch circuit C11110 114) at the
Four data latch controlling transistors 431 to 434 are same time>t0 contro1 the programming operation of the
selected according to a combination of low-order two load transistors (171to 174) when the chip enable signal
bits AO and Al of address input bits AO to An when is made active (CE=0) and a programming power
signal OE is at a high level. Asshown in FIG. 5, in the 60 source voltage (Vpp) is set at the programming voltage
page mode signal PGM and CE are both set to a high (SVpp= 1), while the output enable signal is kept inac
level. At this time, input data Dl to D4 sequentially tive (OE=l). Further, when the output enable signal is
supplied to I/O terminal 41 are respectively latched by made active (OE=0) or the programming power source
latch circuits 441 to 444 via data latch controlling tran- voltage (Vpp) is set at a voltage different from the pro
sistors 431 to 434 which are sequentially turned on each 65 gramming voltage (SVpp=0), the data latch circuits
time signal OE is set to a high level. When signal PGM (111 to 114) are reset. The data latch circuits (111 to
is set to a low level, page mode programming transistors 114) can be selectively specified by a preset combina
451 to 454 are controlled so as to be turned on at the tion of bits (AO, AO, Al, Al).