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CODE ERROR CORRECTING AND
DETECTING APPARATUS
BACKGROUND OF THE INVENTION
The present invention relates to a code error correcting and detecting apparatus and, more particularly, to a code error correcting and detecting apparatus that performs predetermined processes on digital data read from a recording medium, such as a CD (Compact Disc) or a DVD (Digital Video Disc).
In compact disc read only memory (CD-ROM) systems, a digital audio compact disc (CD) functions as a read only memory (ROM) for digital data. To improve the reliability of digital data read from the CD, error correction is per- ^ formed twice on the digital data. The first error correction is executed by a digital signal processor which is common to both an audio system and a CD-ROM system, and the second error correction is executed by a CD-ROM decoder of the CD-ROM system. 20
FIG. 1 is a block diagram of a CD-ROM system. The CD-ROM system includes a pickup 1, a pickup controller 3, an analog signal processor 4, a digital signal processor 5, a CD-ROM decoder 6, a buffer random access memory (RAM) 7 and a control microcomputer 8. 25
The pickup 1 irradiates light on a disk 2 to generate a voltage signal proportional to the intensity of the reflected light. The pickup controller 3 controls the read position of the pickup 1 with respect to the disk 2 so that the pickup 1 reads data from the disk 2 in the correct order. Servo control 30 to turn the disk 2 at a predetermined velocity is performed in accordance with the position control of the pickup 1. The servo control keeps constant the linear velocity of tracks on the disk 2.
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The analog signal processor 4 receives the voltage signal from the pickup 1 and generates one frame of an Eight to Fourteen Modulation (EFM) data signal consisting of 588 bits. As shown in FIG. 2, EFM data includes a 24-bit sync signal assigned to the beginning of each frame, 3-bit connection bit fields and 14-bit data bit fields which are alter- 40 nately provided in each frame after the sync signal.
The digital signal processor 5 receives the EFM signal from the analog signal processor 4 and performs EFM demodulation on the signal for conversion to 8 bits from 14 4J bits. In this EFM demodulation, 8-bit subcode data is produced from the first data bit field following the sync signal, and 32-byte symbol data is produced from the remaining thirty-two pieces of data bit fields. Further, the 32-byte symbol data is subjected to Cross-Interleave Reed- 5Q Solomon Code (CIRC) demodulation to yield one frame of CD-ROM data consisting of 24 bytes. The first error correcting process is completed with this CIRC demodulation.
The CD-ROM data is handled in a block by block manner, each block of data consisting of 2352 bytes (24 bytesx98 55 frames). As shown in FIG. 3, normally (in mode 1), one block of data includes a sync signal (12 bytes), a header (4 bytes), user data (2048 bytes), an error detection code (EDC) (4 bytes) and an error correction code (ECC) (276 bytes). In one block of data, 2340 bytes of data excluding the 12-byte 60 sync signal has previously undergone a scrambling process and is reproduced by a descrambling process.
The CD-ROM decoder 6 receives the CD-ROM data from the digital signal processor 5 and performs error correction in accordance with the ECC and error detection in accor- 65 dance with the EDC to provide the processed CD-ROM data to a host computer. Normally, therefore, after an error in data
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is corrected in accordance with the ECC, it is checked in accordance with the EDC to determine if the error was properly corrected. When the error has not been corrected properly, error correction is carried out again in accordance with the ECC, or an error flag is affixed to the CD-ROM data containing the error code.
The buffer RAM 7 is connected to the CD-ROM decoder 6 and temporarily stores CD-ROM data in a block by block manner. Since the ECC and EDC are included in one block of CD-ROM data, the CD-ROM decoder 6 requires at least one block of CD-ROM data. Therefore, the buffer RAM 7 stores one block of CD-ROM data for the CD-ROM decoder 6.
The control microcomputer 8 can be a one-chip microcomputer that incorporates an internal ROM and an internal RAM. The control microcomputer 8 controls the operation of the CD-ROM decoder 6 in accordance with a control program stored in the ROM. At the same time, the control microcomputer 8 receives command data from the host computer and subcode data from the digital signal processor 5 and temporarily stores those data in its internal RAM. The control microcomputer 8 controls the operations of the individual circuits in accordance with the command data (i.e., commands from the host computer) so that the host computer can receive the desired CD-ROM data from the CD-ROM decoder 6.
The CD-ROM decoder 6 receives the CD-ROM data from the digital signal processor 5 and sends the CD-ROM data to the host computer in parallel. In accordance with the input and output of data, writing and reading the CD-ROM data into and from the buffer RAM 7 are repeated. Normally, the CD-ROM decoder 6, in a time-sharing manner, accesses the buffer RAM 7 in units of bytes or codes for each input or output.
In general, the CD-ROM decoder 6 is configured such that error correction and detection for one block of CD-ROM data is completed within a predetermined period (hereinafter called "one block period") in accordance with a reference system clock. If a predetermined process cannot be accomplished within one block period for some reason, CD-ROM data is consecutively written in the buffer RAM 7. As a result, unprocessed CD-ROM data remains in the buffer RAM 7. As such a state continues, the buffer RAM 7 overflows. This overflow forces the CD-ROM decoder 6 to temporarily interrupt the reception of CD-ROM data.
For fast reproduction like x2 reproduction, the CD-ROM system increases the playback speed of the disk 2 without changing the frequency of the reference system clock supplied to each circuit. The increased playback speed decreases the number of clock cycles supplied in one block period. In other words, the duration of one block period for error correction and detection is shortened and becomes insufficient to find and correct errors, and to process the CD-ROM data. The reduction in the number of clock cycles makes it difficult to complete a predetermined process in one block period.
For fast transfer of CD-ROM data to the host computer, the frequency of data reading from the buffer RAM 7 can be increased. However, when such fast transfer is provided, the time available for reading and writing CD-ROM data from and into the buffer RAM 7 decreases. As a result, the error correction and detection process is often delayed, thus making it difficult to accomplish a predetermined process in one block period.
The above-mentioned problems also arise in a digital video disc read only memory (DVD-ROM) system which
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uses a DVD or a high-density recording medium as a ROM. A DVD has approximately seven times the recording capacity of a CD. Therefore, there is an even greater demand for a faster playback speed in a DVD-ROM system than for a CD-ROM system. 5
It is an object of the present invention to provide an error correcting and detecting decoder that executes a decode process at high speed.
SUMMARY OF THE INVENTION
Briefly stated, the present invention provides a code error correcting and detecting apparatus which performs error correction and error detection on plural blocks of digital data using an error correction code and an error detection code to generate processed digital data. The apparatus includes an 15 input interface, a temporary memory, a correcting circuit, a detecting circuit, a principal memory, and an output interface. The input interface fetches digital data in a block by block manner. The internal memory stores the fetched digital data in a block by block manner. The correcting circuit 20 performs error correction on digital data read from the internal memory in a block by block manner using the error correction code and rewrites erroneous digital data to the internal memory with the corrected digital data. The detecting circuit performs error detection on the error corrected 25 digital data and supplied from the internal memory in a block by block manner using the error detection code and sets an error flag based on a detection result. The principal memory stores, in a block by block manner, the error corrected digital data supplied to the detecting circuit from 30 the internal memory. The output interface transfers the error corrected digital data stored in the principal memory to an external unit.
The present invention also provides a code error correcting and detecting apparatus which performs error correction 35 and error detection on plural blocks of digital data using an error correction code and an error detection code to generate processed digital data. The apparatus includes an input interface, a temporary memory, a principal memory, a correcting circuit, a detecting circuit, and an output interface. 40 The input interface fetches digital data in a block by block manner. The internal memory stores the fetched digital data in a block by block manner. The principal memory stores digital data in a block by block manner together with the internal memory. The correcting circuit performs error cor- 45 rection on digital data read from the internal memory in a block by block manner using the error correction code and rewrites erroneous digital data to the internal memory and the principal memory with correct digital data. The detecting circuit performs error detection on the error corrected digital 50 data supplied from the internal memory in a block by block manner using the error detection code and sets an error flag based on a detection result. The output interface transfers the error corrected digital data stored in the principal memory to an external unit. 55
The present invention can be implemented in numerous ways including as an apparatus, a system and a method.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention, together with objects and advantages 60 thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:
FIG. 1 is a schematic block diagram of a conventional CD-ROM system; 65
FIG. 2 shows the format of data read from a disk by the system in FIG. 1;
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FIG. 3 shows the format of CD-ROM data generated by the system in FIG. 1;
FIG. 4 is a schematic block diagram of a code error correcting and detecting apparatus according to a first embodiment of the present invention;
FIG. 5 is a timing chart of the flow of CD-ROM data processed by the apparatus in FIG. 4;
FIG. 6 shows the constitution and access order of CD-ROM data in an error correcting process performed by the apparatus in FIG. 4;
FIG. 7 is a schematic block diagram of an address generating circuit in accordance with the present invention;
FIG. 8 is a diagram exemplifying access to a temporary memory in the apparatus in FIG. 4;
FIG. 9 is a diagram exemplifying access to a principal memory in the apparatus in FIG. 4;
FIG. 10 is a schematic block diagram of a code error correcting and detecting apparatus according to a second embodiment of the present invention; and
FIG. 11 is a timing chart showing the flow of CD-ROM data processed by the apparatus in FIG. 10.
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENTS
FIG. 4 is a schematic block diagram of a code error correcting and detecting apparatus 100 according to a first embodiment of the present invention. The code error correcting and detecting apparatus 100 has a CD-ROM decoder 10 and a principal memory (buffer RAM) 20. The CD-ROM decoder 10 includes an input interface 11, an error correcting circuit 12, an error detecting circuit 13, an output interface 14, a first memory controller 15, a second memory controller 16 and a temporary memory 17, all integrated on a single semiconductor substrate. In this embodiment, the temporary memory 17 is provided in the CD-ROM decoder 10, and the principal memory 20 is provided outside the CD-ROM decoder. Alternatively, both the temporary memory 17 and the principal memory 20 may be provided in the CD-ROM decoder 10.
The input interface 11 receives CD-ROM data (one block of CD-ROM data consists of 2352 bytes) generated by a digital signal processor (DSP), extracts a sync signal of 12 bytes from the CD-ROM data and generates a block sync signal which indicates the head of each block. The block sync signal is supplied to the individual components of the CD-ROM decoder 10. The input interface 11 descrambles 2340-byte CD-ROM data excluding the sync signal and supplies the descrambled data to the internal memory controller 15.
The error correcting circuit 12 receives CD-ROM data block by block, and performs code error correction using an error correction code (ECC). In the code error correction, one block (2352 bytes) of data is separated into an upperbyte plane (1176 bytes) and a lower-byte plane (1176 bytes). Then, syndrome computation is executed using code words (P and Q) of two systems that are set for the respective planes.
The P code words and Q code words comprise 1032 pieces of symbol data in one plane excluding the sync signal and ECC as shown in FIG. 6. In the symbol data, two P code words are assigned to each 24 pieces of symbol data with respect to the P sequence and two Q code words are assigned to each 43 pieces of symbol data with respect to the Q sequence. Accordingly, 86 P code words are assigned for 43 sets of symbol data, and 52 Q code words for 26 sets of
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