DESCRIPTION OF THE PREFERRED ^2^.^TM^ c\,»nr»ni\/fT3Krrc memory 46 as an effective instruction to an instruction EMBODIMENTS register 48 or to modify the instruction read from the Referring to FIG. 1, there is shown one example of a memory into a different instruction such as a no-operaprocessing unit of a microcomputer, which can incor- 5 tion instruction, which is fed to the instruction register porate therein the program control circuit in accor- 48.
dance with the present invention. The shown process- Operation will be described with reference to the
ing unit 1 includes a CPU internal bus 10 and an input- flow chart shown in FIG. 3.
/output (I/O) device 12 which are coupled between the The repetition number of an operation execution is
CPU internal bus 10 and an externa) bus 14, which is 10 set to the register 40, and then transferred to the counter
coupled to an instruction read only memory (ROM) 36 42. On the other hand, a sequence of instructions stored
of a microcomputer. Furthermore, the CPU internal in the memory 46 is made such that a signal S is gener
bus 10 has coupled thereto an accumulator 16, a tempo- ated when an instruction just before a jump instruction
rary register 18 and a status register 20. Outputs of the for operation repetition is executed or set in the instruc
accumulator 16 and the temporary register 18 are cou- 15 tion register 48. Thus, an instruction is sequentially read
pled to inputs of an arithmetic and logic unit (ALU) 22 out from the memory 46 and is transferred through the
which is controlled by the status register 20. An output instruction controller 44 to the instruction register 48 if
of the ALU 22 is coupled to the CPU internal bus 10. the counter 42 generates neither a borrow signal nor a
These elements (16 to 22) carry out the arithmetic logi- carry signal, so that the instruction set in the instruction
cal processing. 20 register 48 is sequentially executed. When instructions
The shown processing unit 1 also comprises an in- excluding the instruction just before the jump instrucstruction register 24 having an input coupled to the tion are executed, since the signal S is not generated, the CPU internal bus 10 and an output coupled to an input value of the counter 42 is maintained as it is. Therefore, of an instruction decoder 26. The instruction decoder 26 neither a borrow signal nor a carry signal is outputted supplies its output to a timing controller 28 for supply- 25 from the counter 42, the instruction is read from the ing and receiving various kinds of control signals. In memory 46 and then transferred as it is through the addition, there is a group of registers 32 including a instruction controller 44 to the instruction register 48. program counter, which register group is coupled be- But, when the instruction just before the jump instructween the CPU internal bus 10 and an address buffer 34 tion is executed, a signal S of a logical level "1" is suphaving an output coupled to an address bus 30 of the 30 plied to the counter 42 so as to decrement the counter microcomputer. 42 in the case that the counter 42 is of the decrement
In operation, the shown processing unit will operate type,
in a manner similar to that of a conventional processing As the result of the decrement of the counter 42, if the
unit. counter 42 does not generate a borrow signal, the in
Briefly, the timing controller 28 generates timing 35 struction controller 44 supplies the instruction, i.e., the
signals and operates on the basis of the generated timing jump instruction, stored in the memory 46 to the in
signals and various kinds of control signals received struction register 48, so that the jump instruction will be
from the instruction decoder 26 so as to control the executed. In other words, the operation is returned to
turn-on and turn-off of various gates (not shown) in the the repetition sequence including a plurality of instruc
processing unit and at the same time to cause the ad- 40 tions. Thus, the operation which has already been exe
dress buffer 34 to supply the address and data onto the cuted one time will be executed again. As a result, when
address bus 30. Also, the timing controller 26 operates the instruction just before the jump instruction is exe
to control transfer of various control signals between cuted again, the signal S is generated again so as to
the I/O ports 30 and the external bus 14. On the other decrement the counter 42.
hand, the instruction is fed from the external bus 14 to 45 Such a repeated execution of the same operation is the I/O device 12 and is written to the instruction regis- performed until the counter 42 generates a borrow sigter 24 through the CPU internal bus 10. The written nal. Then, the instruction controller 44 modifies the instruction is decoded by the instruction decoder 26 and instruction, i.e., the jump instruction read from the then furnished to the timing controller 28. memory to a no-operation instruction, and supplies the Turning to FIG. 2, there is shown one embodiment of 50 no-operation instruction to the instruction register 48. the program control circuit in accordance with the Asa result, the jump instruction is not executed, and so, present invention, which can be located between the the operation goes out of the repeated operation. Thereinternal bus 10 and the instruction register 24 or the I/O after, an instruction next to the jump instruction is read device 12 in the processing unit shown in FIG. 1. The from the memory 46 and transferred through the inshown program control circuit comprises a register 40 55 struction controller 44 to the instructions register 48 so adapted to be stored with information necessary for that the next instruction will be executed, program control, such as the repetition number of a If the counter 42 is of the increment type, the counter program operation to be repeatedly executed. A con- 42 is incremented in response to the signal S, and until tent of the register 40 is sent to a counter 42, which is in the counter 42 generates a carry signal, the instructions turn decremented or incremented in response to a signal 60 read out of the memory 46 are fed without modification S. When the counter 42 is of the count-down type it will to the instruction register 48, so that, if a jump instrucgenerate a borrow signal to an instruction controller 44. tion is contained in the instructions read from the memWhen the counter 42 is of the count-up type, it will ory 46, an operation will be repeatedly performed in generate a carry signal to the instruction controller 44. accordance with the jump instruction. This instruction controller 44 is coupled to a memory 46 65 As seen from the above, the instructions to be exestoring a sequence of programmed instructions, which cuted are controlled in accordance with the output corresponds to the instruction ROM 36. The controller (borrow or carry) of the counter 42, so that a repeated 44 is adapted to respond to the output signal of the operation execution is selectively allowed or inhibited.