METHOD FOR FORMING SILICON-
GERMAMUM/S I/SILICON DIOXIDE
HETEROSTRUCTURE USING GERMANIUM
Field of the Invention
The invention relates generally to the fabrication of semiconductor devices. The invention relates more specifically to a method for forming a high quality insulator in combination with GeSi or another mobility enhancing material having a charge carrier mobility that is greater than the charge carrier mobility of silicon.
Cross Reference to Related Applications
The following copending U.S. patent applications are assigned to the assignee of the present application, are related to the present application and their disclosures are incorporated herein by reference:
(A) Ser. No. 07/861.141 filed Mar. 31, 1992 by Tatsuo Nakato and entitled, GRADED IMPLANTATION OF OXYGEN AND/OR NITROGEN CONSTITUENTS TO DEFINE BURIED ISOLATION REGION IN SEMICONDUCTOR DEVICES;
(B) Ser. No. 08/028.832 filed Mar. 10.1993 now U.S. Pat. No. 5.278,077. by Tatsuo Nakato and entitled, PESTHOLE PATCH METHOD FOR IMPLANTED DIELECTRIC LAYER; and
(C) Ser. No. 08/049,735 filed Apr. 20. 1993, now abandoned, by Sheng Teng Hsu and Tatsuo Nakato and entitled. Ge—Si SOI MOS TRANSISTOR AND METHOD OF FABRICATING SAME.
Cross Reference to Related Other Publications
The following publications are believed to be related to the present application and are cited here for purposes of reference:
(a) S. Verdonckt-Vandebroek et al (IBM). "Design Issues for SiGe hetero-junction FETs," IEEE 1991, pp 425-434 (Full citation not known.)
(b) E. Murakami et al. "Strain-Controlled Si—Ge Modulation-doped FET with Ultrahigh Hole Mobility," IEEE Electron Device Letters, Vol. 12, No. 2, February 1991;
(c) S. S. Iyer et al.. "A Gate-Quality Dielectric System for SiGe Metal-Oxide-Semiconductor Device," IEEE Electron Device Letters, Vol. 12, No. 5. May 1991;
(d) P. M. Garone et al., "Hole Confinement in MOS-Gated Ge^ii^Si Heterostinctures." IEF.F. Electron Device Letters, Vol. 12, No. 5, May 1991;
(e) C. R. Selvakumar et al., "SiGe-Channel M-MOSFET By Germanium Implantation" IEEE Electron Device Letters, Vol. 12, No. 5, August 1991;
(f) A. R. Srivatas et al., "Nature of Interfaces and Oxidation Processes in Ge+ Implanted Si," J. Appl. Physics 65(10) 15 May, 1989, pp 4028-W32.
Description of the Related Art
Silicon (Si) is commonly selected as the bulk material for fabricating semiconductor devices. This is done in spite of the fact that other materials such as Germanium (Ge) generally exhibit higher electron and hole mobilities. (Electron and hole mobilities in Ge are approximately 3 to
5 times that of Si.) The performance of silicon-based integrated circuits would be significantly enhanced if a practical method could be found for replacing the slower charge mobilities of silicon with the faster ones of high mobility
5 materials such as Ge.
Unfortunately this is not easily done. One cannot simply substitute Ge for Si because Ge has its own set of problems. Ge suffers from relatively poor thermal conductivity and relatively high leakage currents. Another problem of Ge is
io that its oxide, Ge02. has a very low breakdown voltage and thus, can not serve as a practical insulator.
Attempts to mix a better insulator such as Si02 with an adjacent layer of a Ge-containing material (e.g.. an SiGe hetero-layer) suffer from the problem that high-density
15 interface-states tend to form at interfaces between silicon oxides (e.g.. Si02) and materials such as Ge and Ge^i^ The high-density interface-states disadvantageously reduce electron/hole mobilities. In order to reduce the interface-state problem, a tri-layer
20 heterostructure of the form: GeJJi^Si/SK^ has been proposed. (See for example, the above cited work of S. Verdonckt-Vandebroek et al (IBM), "Design Issues for SiGe hetero-junction FETs." IEEE 1991.)
25 The ... portion of the tri-layer heterostructure is advantageously used for its higher electron and hole mobilities. The Si portion is used for its ability to provide reduced interface-states at the interface with the Si02 dielectric material.
30 The problem with previous tri-layer proposals, however, is that they employ relatively complex and costly fabrication methods for the creation of the GeJSij.^Si/SiOj heterostructure; such as high-vacuum CVD or epitaxial growth of the Ge^Si^ySi layers. (See the Introduction in the above cited
35 paper by C. R. Selvakumar et al., "SiGe-Channel M-MOSFET By Germanium Implantation" IEEE 1991.)
SUMMARY OF THE INVENTION
The invention overcomes the above-mentioned problems
40 by providing a fabrication method in which a mobility enhancing species such as Ge is implanted into a portion of a low-mobility, monocrystalline material such as monocrystalline Si to define a mobility-enhanced heterostructure such as a Ge^i^Si heterostructure. The Ge implant is prefer
45 ably graded in concentration, with high concentration (e.g., 25%) near the Si portion of the Ge^Si^Si heterostructure and lesser concentration (e.g., 15%) as one moves away from the Si portion. The juncture of the mobility-enhanced portion (e.g., the
so Ge^Sii., portion) of the heterostructure and adjacent Si (e.g.. an overlying Si cap) defines an interface which is free of the interface-state problem found at GejeSi1_J/Si02 junctures. A silicon portion of the Ge^i^Si heterostructure that is spaced away from the Ge^i^^/Si juncture is oxidized to
55 form a high quality dielectric that is spaced apart from the mobility-enhanced portion (e.g., the Ge^Si^ portion) by a region of monocrystalline silicon, thus forming a GeJii^J Si/Si02 heterostructure. Because the Si portion of the Ge^Si^j/Si/SiOz heterostructure is part of the original,
60 monocrystalline monostructure into which the Ge was implanted; the Si portion remains generally free of undesirable stacking faults. Avoidance of stacking faults leads to improved device performance.
A method for fabricating a GeSi/Si/Sio2 heterostructure in
65 accordance with the invention comprises the steps of: (a) providing a monocrystalline Si substrate; (b) defining a GeJSi,.,. region within the Si substrate by implanting a