QUALITY OF SERVICE (QOS) PROCESSING
OF DATA PACKETS
The present disclosure relates to processing of data packets, and, more particularly, to Quality of Service (QoS) processing of data packets.
BRIEF DESCRIPTION OF THE DRAWINGS i o
The advantages and features of the present disclosure will become better understood with reference to the following detailed description and claims taken in conjunction with the accompanying drawings, wherein like elements are identified 15 with like symbols, and in which:
FIG. 1 illustrates a system for providing Quality of Service (QoS) processing of a plurality of data packets, according to an exemplary embodiment of the present disclosure;
FIG. 2 is a flowchart illustrating a method for providing 20 QoS processing of the plurality of data packets, according to an exemplary embodiment of the present disclosure;
FIG. 3 is a flowchart illustrating a software flow of the method for providing QoS processing of the plurality of data packets, according to an embodiment of the present disclo- 25 sure;
FIGS. 4A and 4B illustrate examples of QoS processing of data packets;
FIG. 5 illustrates a system for providing dynamic priority to the data packets, according to an exemplary embodiment of 30 the present disclosure;
FIG. 6 is a flowchart illustrating a software flow of a method for providing dynamic priorities to the data packets, according to an exemplary embodiment of the present disclosure; and 35
FIGS. 7A and 7B illustrate examples of QoS processing of data packets having dynamic priorities.
Like reference numerals refer to like parts throughout the description of several views of the drawings.
DETAILED DESCRIPTION OF THE
For a thorough understanding of the present disclosure, reference should be made to the following detailed descrip- 45 tion, including the appended claims, in connection with the above-described drawings. Although the present disclosure is described in connection with exemplary embodiments, the disclosure is not intended to be limited to the specific forms set forth herein. It is understood that various omissions and 50 substitutions of equivalents are contemplated as circumstances may suggest or render expedient, but are also intended to cover the application or implementation without departing from the spirit or scope of the claims of the present disclosure. Also, it should be understood that the phraseology and termi- 55 nology used herein is for the purpose of description and should not be regarded as limiting.
The terms "first," "second," and the like herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, and the terms "a" 60 and "an" herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item.
FIG. 1 illustrates a system for providing Quality of Service (QoS) processing for a plurality of data packets 128. As used 65 herein, QoS refers to a control mechanism for providing different priorities to data packets and a mechanism for ensur
ing a certain level of performance, while processing of data packets. The system comprises a Network Processing Engine (NPE) 102, a bridge 104, a Memory controller 106, an external Dynamic Random Access Memory (DRAM) 108, a queue manager module 110, a processor/low power IA core 112, a Static Random Access Memory (SRAM) 114, a counter 116.
The NPE 102 receives the plurality of data packets 128 for processing. The NPE 102 is a routing engine for providing modular and evolutionary performance scaling capabilities. The plurality of data packets received at the NPE 102 is stored in the external DRAM 108. However, the data packets may also be stored in a cache memory, SRAM or any other memory. The plurality of data packets 128 may be stored along with their header information in the external DRAM 108. An address of each data packet of the plurality of data packets 128 is stored in a plurality of queues in a queue manager module 110.
Each queue of the plurality of queues corresponds to a particular priority. For example, a queue 118 includes addresses of at least one data packet having the highest priority, a queue 122 includes addresses of at least one data packet having the least priority, and a queue 120 includes address of at least one data packet having an intermediate priority. Further, the number of queues maintained in the queue manager module 110 is scalable. The queue manager module 110 further comprises an interrupt status register 124 and a logical OR circuitry 126. The interrupt status register 124 is connected to the queues and each bit of the interrupt status register 124 specifies a queue of the plurality of queues causing an interrupt.
A queue causing an interrupt asserts the willingness for processing of the at least one data packet whose address are stored in the queue. For example, if the queue 118 causes an interrupt, then contents of the interrupt status register 124 will indicate that the queue 118 is requesting for process of the at least one data packet whose address are stored in the queue 118. The number of address of data packets that can be stored in the queue is a predefined value. The predefined value may be inputted by a user or specified by the system administrator. The logical OR circuitry 126 may perform a bit wise logical OR operation with the contents of the interrupt status register 124 and sends the interrupt to the processor 112 and the counter 116. The processor 112 may include a register/cache memory 130. The cache memory 130 stores a base address of a plurality of interrupt masks 132,134,136 and 138 stored in the SRAM 114. The plurality of interrupt masks 132, 134, 136,138 are stored in consecutive memory locations starting from the base address. An interrupt mask is used for suppressing a certain interrupt and allowing the processor 112 to handle these interrupts later. The interrupt mask specifies whether the interrupt can be processed or not after an interrupt has occurred. Each interrupt of the plurality of interrupts corresponds to a queue of the plurality of queues. Accordingly, the length of interrupt masks stored in the SRAM 114 may equal the number of queues in the queue manager module 110.
The processor 112 may periodically perform a logical operation between the plurality of interrupt masks 132, 134, 136 and 138 stored in the SRAM 114 and the contents of the interrupt status register 124 sent to the processor 112 after processor 112 receives an interrupt from the Logical OR circuitry 126. The Logical OR circuitry 126 combines all interrupts from queues into one interrupt and sends the interrupt to processor 112 and counter 116 when any one or more queues request for service. Since queues assert their interrupt by updating their respective status bits in the interrupt status register, performing a bit wise Logical OR on the contents of