VIA CONFIGURABLE ARCHITECTURE FOR
CUSTOMIZATION OF ANALOG CIRCUITRY
IN A SEMICONDUCTOR DEVICE
 This application is a Divisional of U.S. patent application Ser. No. 10/907,456, filed Apr. 1, 2005, now U.S.
patent Ser. No. , which claims priority to provisional
patent application Ser. No. 60/559,400, filed Apr. 2, 2004. The entire disclosures of the above-identified applications are incorporated herein by reference.
 Application specific integrated circuits (ASICs) have been available for a number of years. A full-custom ASIC is a device which requires all layers in a semiconductor process to be created in a custom fashion. The process of creating a full-custom ASIC is costly, time consuming, and error prone. Throughout the years much effort has been put in to minimizing the drawbacks of full-custom ASICs. The gate array was created for smaller logic designs where the base chip came as an array of standard digital cells (e.g. AND, OR, and NAND gates). The final product was realized by adding the layers required to interconnect these standard cells to realize a particular function. A gate array is considered a semi-custom ASIC. Some time after gate arrays came field programmable gate arrays (FPGAs). As the name implies, the FPGA all but eliminated the custom portion of the design process. By virtue of their field programmability, there is no fabrication in the development process. However, FPGA technology is not able to compete with full-custom ASIC technology on performance and device cost. More recently, the use of gate arrays has increased with the advent of structured array technology which is essentially equivalent to gate arrays, but on a much larger scale. Most structured arrays minimize the number of layers that have to be configured, yet still offer significant performance and device cost advantages when compared to FPGAs.
 Thus far, structured array technology has focused on all digital devices. Most structured arrays combine large numbers of logic circuits into a logic cell to create a device that is specifically adapted for a particular application, but at a cost that is lower than that of developing a completely new device from scratch. Like most integrated circuits, structured arrays are manufactured using a lithographic process that depends on having a mask for each layer of the chip. Some masks may be generic, but others are custom. It is the custom masks that impart the application specificity to the chip by programming the logic cells during the manufacturing process. Reducing the number of custom masks to just one mask provides significant cost and time savings. A "one mask" device allows all of the masks to remain generic except for a single mask, thus allowing the semiconductor manufacturer to invest in the generic or base masks just one time. Various designs may be implemented by customizing just a single mask instead of a complete mask set.
 The present invention provides for a semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. In exemplary embodiments, the plurality of layers may include three metal layers, one polysilicon layer, and one via layer. At least one of the plurality of
layers in the semiconductor device is a via layer configured to determine the interconnection of the plurality of circuit elements. The plurality of circuit elements may be analog circuit elements and/or digital circuit elements that are arranged into analog tiles and digital tiles that form a mixed signal structured array.
 In some embodiments, the semiconductor device includes an interconnection quilt that has a plurality of metal layers disposed to interconnect the plurality of circuit elements. The interconnection quilt may configure the semiconductor device using at least one of the plurality of layers.  The inclusion of analog circuit elements with digital circuit elements such as those described above creates a "mixed signal" device that can facilitate a wide variety of analog functions such as gain stages, filters, and modulators. By making the analog and digital configurable with single layer configurability a "one mask mixed signal structure array" can be implemented resulting in a semi-custom mixed signal solution for a fraction of the cost and development time.
BRIEF DESCRIPTION OF THE DRAWINGS
 FIG. 1 provides a schematic diagram representing a circuit according to at least some embodiments of the present invention.
 FIG. 2 illustrates a side view of the semiconductor layers forming the circuitry of FIG. 1 according to at least some embodiments of the present invention.  FIG. 3 illustrates the metal 2 and 3 layers forming the circuitry of FIG. 1 according to at least some embodiments of the present invention.
 FIG. 4 illustrates an analog tile according to at least some embodiments of the present invention.  FIG. 5 illustrates an analog structured array formed by several analog tiles according to at least some embodiments of the present invention.
 FIG. 6 provides a schematic diagram representing an operational amplifier according to at least some embodiments of the present invention.
 FIG. 7 provides a schematic diagram representing an analog tile configured to form the circuitry of FIG. 6 according to at least some embodiments of the present invention.
 FIG. 8 provides a schematic diagram representing a Sallen-Key Low-Pass Filter according to at least some embodiments of the present invention.  FIG. 9 provides a schematic diagram representing an analog tile configured to form the circuitry of FIG. 8 according to at least some embodiments of the present invention.
 FIG. 10 illustrates a mixed signal structured array according to at least some embodiments of the present invention.
DESCRIPTION OF THE INVENTION
 It is to be understood that the present invention is not limited to the example embodiments disclosed herein. The meaning of certain terms as used in the context of this disclosure should be understood as follows. The term "metal layer" refers to any layers that are used to make connections between various elements within a device. The metal layers may contain actual metal routing traces, contacts, orvias. Aviamaybe formed by etching material as defined by a mask layer in the