ROM STRUCTURE AND METHOD OF
CROSS-REFERENCE TO RELATED
This application claims the priority benefit of Taiwan application serial no. 87101266, filed Feb. 3, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a type of semiconductor device. More particularly, the present invention relates to a method for manufacturing flash memory cells.
2. Description of Related Art
Read-only memory (ROM) is a type of non-volatile memory. Any data programmed into the memory is not be erased when the power source is cut off. Erasable programmable ROM (EPROM) is another type of ROM whose stored data can be erased so that fresh data can be re-programmed in. However, the erasing operation requires ultra-violet light and so packaging cost is high. Moreover, in a data-erasing operation, all the data stored within the memory is wiped out and every bit of data has to be re-entered, which is rather time-consuming. Even only minor alterations to the data inside the EPROM require complete reprogramming.
Another type of ROM that also permits the erase of stored data is the electrically erasable programmable ROM (EEPROM). Instead of totally erasing all the data inside the memory as in an EPROM, data can be erased and re-programmed in a bit-by-bit manner. Furthermore, data can be stored, read out or erased many times in its working life. In recent years, a faster version of EEPROM has developed; its storage/retrieval time is between 70 ns to 80 ns. The U.S. firm Intel coined the name, "flash memory", for this type of memory. Flash memory has a structure similar to an EEPROM. The main difference is in the way memory is erased. The memory inside an EEPROM is erased in a block-by-block manner, and hence the erasing speed can be very fast. Whole chunks of memory can be erased in just one or two seconds, and so much reprogramming time can be saved.
FIG. la is a top view showing the transistor memory structure of a conventional flash memory. In FIG. la, label S represents the source region of a transistor while label D represents the gate region of the transistor. The cells are arranged in such a way that a group of 16 memory units is joined to the same contact opening. FIG. lb is a crosssectional view along line AA of FIG. la showing a memory unit. The memory unit of a flash memory is constructed from a floating transistor having a basic two-layer structure. One of the layers is a floating gate layer 10. The floating gate layer 10 is fabricated from a polysilicon material and is used for charge storage. The other layer is a control gate 12. The control gate 12 is used for controlling data storage and retrieval. Furthermore, the transistor also includes a tunnel oxide layer 14, a drain region 16, a source region 18 and a deeply doped source region 20. The floating gate 10 is located below the control gate 12. In general, the floating gate 10 is unconnected to any other circuits, hence remaining in a floating state, and the control gate 12 is connected to a word line.
The floating transistor utilizes channel hot electrons in the channel to operate. To store a bit of data, a first voltage is
applied to the drain region 16 of the semiconductor substrate 22 and a second voltage higher than the first voltage is applied to the control gate 12. Hot electrons then flow out from the source region 18, tunnel through the tunneling
5 oxide layer 14 in the neighborhood of the drain region 16, and finally inject into the floating gate 10. With electrons injected into the floating gate 10, the threshold voltage of this floating transistor is increased and the goal of data storage is achieved. To erase a bit of data, a positive voltage of appropriate magnitude is applied to the source region 18. Electrons trapped within the floating gate 10 are then able to flow out via the tunneling oxide layer 14. In this manner, the memory bit is erased and the floating transistor is returned to its previous state.
FIGS. 2a and 2b are cross-sectional views showing the
15 progression of manufacturing steps in forming a conventional flash memory. First, as shown in FIG. 2a, a semiconductor substrate 100 is provided. Next, a thin tunneling oxide layer 120, preferably having a thickness less than 100 A, is formed over the semiconductor substrate 100 using, for
20 example, a thermal oxidation method. The tunneling oxide layer 120 generally has a high dielectric constant, a low oxide charge and a high breakdown voltage. Thereafter, a first polysilicon layer 140 is deposited over the tunneling oxide layer 120, and then the polysilicon layer 140 is
25 patterned to form a floating gate. Subsequently, a dielectric layer 160 having, for example, an oxide/nitride/oxide (ONO) multi-layered structure is formed over the first polysilicon layer 140. A second polysilicon layer 180 is deposited over the dielectric layer 160, and then the second
30 polysilicon layer 180 is patterned forming the stacked gate structure 200 of a flash memory.
Next, as shown in FIG. 2b, an ion implantation is carried out implanting N-type ions, such as arsenic (As) ions, into the semiconductor substrate 100. Consequently, a heavily doped region is formed on each side of the stacked gate
35 structure 200. The two heavily doped regions are the respective source/drain regions 220.
In the above conventional method of forming a flash memory, no etching barrier layers are erected prior to either the patterning of the first polysilicon layer to form the
40 floating gate or patterning the second polysilicon layer to form the control gate. Therefore, during the process of removing portions of the first polysilicon layer or the second polysilicon layer, over-etching may occur resulting in the formation of trenches in the source regions, as shown in FIG.
45 la 13 area. Conventionally, there are a few technical methods of dealing with the over-etching problem. One method is to rely on the fabrication process itself to control the trench depth. However, this method is rather unreliable because it is very difficult to precisely control the etching
5q depth; it is further limited by junction depth in the source/ drain regions. Another method is to pattern with a mask and then perform an arsenic implantation targeting the trench locations so that a sufficiently thick layer of etching barrier layer is produced. However, this method requires additional mask-making operations, thereby complicating the fabrication process. In a third method, the floating gate itself acts as a mask when arsenic implantation is performed so that no additional mask making steps are required. However, in this case, an oxide etching barrier layer will be formed on the sidewall of the floating gate. This thick oxide layer along the
60 sidewalk of the floating gate lowers the coupling rate between the floating gate and the control gate.
In light of the foregoing, there is a need to improve the method of manufacturing flash memory.
65 SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a ROM structure having spacers on the sidewalk of the floating gate