ACCUMULATE HARDWARE CO-
This application claims priority under 35 USC §119(e) (1) of Provisional Application No. 60/073,641, filed Feb. 4, 1998.
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is digital signal processing and particularly a digital signal processor with a core data processor and a reconfigurable co-processor.
BACKGROUND OF THE INVENTION
Digital signal processing is becoming more and more common for audio and video processing. In many instances a single digital processor can replace a host of prior discrete analog components. The increase in processing capacity afforded by digital signal processors had enabled more types of devices and more functions for prior devices. This process has created the appetite for more complex functions and features on current devices and new types of devices. In some cases this appetite has outstripped the ability to cost effectively deliver the desired functionality with full programmable digital signal processors.
One response to this need is to couple a digital signal processor with an application specific integrated circuit (ASIC). The digital signal processor is programmed to handle control functions and some signal processing. The full programmability of the digital signal processor enables product differentiation through different programming. The ASIC is constructed to provide processing hardware for certain core functions that are commonly performed and time critical. With the increasing density of integrated circuits it is now becoming possible to place a digital signal processor and an ASIC hardware co-processor on the same chip.
This approach has two problems. This approach rarely results in an efficient connection between the hardware co-processor ASIC and the digital signal processor. It is typical to handle most of the interface by programming the digital signal processor. In many cases the digital signal processor must supply data pointers and commands in real time as the hardware co-processor is operating. To form safe designs, it is typical to provide extra time for the digital signal processor to service the hardware co-processor. This means that the hardware co-processor is not fully used. As second problem comes from the time to design problem. With the increasing capability to design differing functionality, the product cycles have been reduced. This puts a premium on designing new functions quickly. The ability to reuse programs and interfaces would aid in shortening design cycles. However, the fixed functions implemented in the ASIC hardware co-processor cannot be easily be reused. The typical ASIC hardware co-processor has a limited set of functions suitable for a narrow range of problems. These designs cannot be quickly reused even to implement closely related functions. In addition the interface between the digital signal processor and the ASIC hardware co-processor tends to use ad hoc techniques that are specific to a particular product.
SUMMARY OF THE INVENTION
This invention is a reconfigurable co-processor adapted for multiple multiply-accumulate operations. The
co-processor includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The
5 co-processor includes sign extend circuits at the output of each multiplier. The sign extend circuits sign extend the product outputs to more than twice the multiplier input width. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of
10 bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair
15 select the product, the right shifted product or pass through the inputs. Selection of the pass through inputs enables A+B*C computations, which are useful in coefficient updates, by bypassing one of the multipliers. The sign extend circuit for the second multiplier follows the multi
Third adders receive the sum outputs of the second adders and produce a third sum output. These third adders include plural selectable output accumulators and variable right shifter at their outputs. The third adders may separately sum 25 the product sums from four multipliers each. Alternatively, the third adders may accumulate the products of eight multipliers.
Special provisions are made for fast Fourier Transforms.
Apair of additional inputs and a pair of additional adders are 30 provided. The first additional input is supplied to a pair of
adders along with a corresponding second sum. The second
additional input is supplied to a second pair of adders along
with another second sum.
The organization permits the same basic hardware to be 35 configured for real and complex finite impulse response
(FIR) filters, fast Fourier transforms (FFT) and coefficient
BRIEF DESCRIPTION OF THE DRAWINGS
40 These and other aspects of this invention are illustrated in the drawings, in which:
FIG. 1 illustrates the combination of a digital signal processor core and a reconfigurable hardware co-processor in accordance with this invention; 45 FIG. 2 illustrates the memory map logical coupling between the digital signal processor core and the reconfigurable hardware co-processor of this invention;
FIG. 3 illustrates a manner of using the reconfigurable hardware co-processor memory; 50 FIG. 4 illustrates a memory management technique useful for filter algorithms;
FIG. 5 illustrates an alternative embodiment of the combination of FIG. 1 including two co-processors with a 55 private bus between;
FIG. 6 illustrates the construction of a hardware co-processor which is reconfigurable to perform a variety of filter functions;
FIG. 7 illustrates the input formatter of the reconfigurable 60 hardware co-processor illustrated in FIG. 6;
FIG. 8 illustrates the reconfigurable data path core of the reconfigurable hardware co-processor illustrated in FIG. 6;
FIG. 9 illustrates the output formatter of the reconfigurable hardware co-processor illustrated in FIG. 6; 65 FIG. 10 illustrates the data flow connections through the data path core for performing a real finite impulse response filter;