loaded with new data from the random array. The SAM SAM DATA SELECTION ON DUAL-PORTED is loaded by executing a special memory cycle called a
DRAM DEVICES read data transfer which copies an entire row or a por
tion of a row of the data to be sequentially clocked out CROSS-REFERENCE TO RELATED 5 Df the SAM into circuitry which updates the screen.
APPLICATION Second generation VRAMs were enhanced with the
This is a continuation-in-part of application Ser. No. ability to transfer data from the DRAM array into half 07/352,442 filed May 16, 1989, entitled "VIDEO RAM of the SAM, while the other half of the SAM is being DOUBLE BUFFER SELECT CONTROL", U.S. Pat. scanned out to the display. This is known as a split read No. 5,065,368. 10 transfer. An output status pin known as QSF is some
. T _. times provided to indicate the half of the SAM being
The present invention relates to semiconductor mem- In some systems there are two frame buffers, with one ories, and more particularly to the selection of data being scanned out to the screen while the other is being stored in dual-port memories. 15 updated by the graphics or image processor. This is
BACKGROUND ART frequently referred to as a double buffered system. The
use of two buffers avoids the problem of scanning a
Dual-ported dynamic random access memory partially updated image to the screen resulting in unde(DRAM) devices are used, for example, for storing skable nial im In doubk bufTered systems, the picture data to be input to a cathode ray tube. The 20 twQ frame buffers are referred t0 „ frame buffer A> picture data is randomly accessed to write or update the FBA and frame buffer fi FBB image in memory and then subsequently accessed sen- Q appiication of graphics displays is to segment the ally to generate the image on a cathode ray tube. A • . i c ■ A \- u A
memory of this type can store images captured by a *=re,en a P1"*11* of w,"dows w*ich *5e mdepr video camera or other scanning device or it may be used 25 dent portions of the screen. Since each window is indeto store images generated by a graphics system. pendent of the others, the current update buffer and the
The image to be displayed is divided into a number of dlsPlav buffer mav dlffer for different windows, pus, discrete picture elements or pixels. Each pixel repre- at anv moment m time, one window can be using frame sents a physical position on the output display monitor buffer A for uPdate and frame buffer B for dlsPlav whlle and can have associated with it a color or specific shade 30 another window can be using the reverse. This leads to of gray. In image and graphics systems, the pixels of a the requirement that the scan out buffer be selectable on display are each represented by a value stored in the a per pixel basis.
memory device. This memory representation of a dis- A graphics system that does not employ windowing, play is typically referred to as a frame buffer. A high may have a single full screen display 100 as shown in resolution display typically has an image of 1280 X1024 35 FIG. IA. The contents of one frame buffer, for example or 1,310,720 pixels. Each pixel value can be represented frame buffer B, is displayed while the contents of a by 1 to 24 or more bits thus requiring a large amount of second one, frame buffer A is updated. At a certain memory to store the image. This requirement for large point in time, the designation of the buffers is swapped amount of high speed memory leads to the use of the so that the contents of frame buffer A is displayed while highest density memory parts available for graphic 40 the contents of frame buffer B is updated, system devices. Typically, DRAMs provide the highest FIG. IB illustrates the use of a windowed system, memory density. Due to the nature of video display puu XTttn ioo may be made up of windows such as scan patterns and update rates, a need for even faster those labeled 102; 104 and 106. Each application will access times and a need to decouple the updating of the maintain an indication of which frame buffer is being frame buffer from the scanning out of the stored values 45 used for u^ate and which is ^ used for di lay (through video generation circuitry) for display on the Imtially window 1 may be with updating
video monitor was realized. frame buffer A, window 2 frame buffer B, and window
Video Random Access Memories (VRAM) are a 3 frame buffer A The ^ di k fa window 1 from
specia .zed form of DRAMs. They were designed to frame buffer B win(Jow 2 ^ fnmje feuffer ^
solve the problem of simultaneously displaying the con- 50.. ,f , w «• r> Tt *i. c
. . , r c , „ . ,l window 3 from frame buffer B. Upon the swapping of
tents of a graphics frame buffer to the screen while ., ,, x r , ~. _, . r ■ J <•
„„ • • . . window 3 between frame buffers, updates for window 1
allowing the graphics or image processor to update the . . , „ . . , '*, , _ „
frame buffer with new data. Video RAMs contain two are mto frame bn^£> TMndTM 2 ^f. B, and
Input/Output ports (one for random access and one for )vmdow * frame, bufferL B> whA,le thf ... » from
serial access) and one address port. These memories are 55 frame bufJer B' frame buffer A' and frame bufFer A'
frequently referred to as dual-port memories. In addi- respectively.
tion to the standard DRAM random access array of °ne method of implementing double buffered sysrows and columns, a serial access memory (SAM) regis- tems ls to Put the two frame buffers m separate ter has been added to support serial input and output. VRAMs. With separate VRAMs it is relatively easy to Video RAMs of this type are known in the prior art, 60 synchronize the two SAM registers and select pixel data for example U.S. Pat. No. 4,541,075 to Dill, et al., de- from one or the other VRAM on a per pixel basis. This scribes such a memory device. The graphics or image c*n be done, for example, by using the Serial Output processor updates the frame buffer by writing into the Enable control pin to only enable the data from the random access array. The serial access memory register desired frame buffer. However, by placing the' frame is designed to sequentially shift the contents of its buffer 65 buffers in separate VRAMS, the cost of the frame buffer to the display independently of the random access ar- will be increased or the drawing rate to the frame buffer ray. The only time the random array and the SAM do will be reduced. Additionally, this design can lead to not operate independently is when the SAM needs to be problems with bus contention if the turn on time of the