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PROCESSOR WHICH CAN BE USED FOR
FIBRE CHANNEL FRAMES
BACKGROUND OF THE INVENTION 5
1. Field of the Invention
This invention relates to devices for transferring data in computer networks, and more particularly to a device for receiving, generating and transmitting frames of data across 10 a computer network boundary.
2. Description of Related Art
The number of computers and peripherals has mushroomed in recent years. This has created a need for improved methods of interconnecting these devices. A wide variety of 15 networking paradigms have been developed to enable different kinds of computers and peripheral components to communicate with each other.
There exists a bottleneck in the speed with which data can be exchanged along such networks. This is not surprising 20 because increases in network architecture speeds have not is kept pace with faster computer processing speeds. The processing power of computer chips has historically doubled about every 18 months, creating increasingly powerful machines and bandwidth hungry applications. It has been 25 estimated that one megabit per second of input/output is generally required per "MIPs" (millions of instructions per second) of processing power. With CPUs now easily exceeding 200 MIPs, it is difficult for network architecture to keep up with these faster speeds. 30
Area-wide networks (e.g., LANs and WANs) and channels are two approaches that have been developed for computer network architectures. Traditional networks offer a great deal of flexibility and relatively long distance capa- 3J bilities. Channels, such as Enterprise System Connection (ESCON) and Small Computer System Interface (SCSI), have been developed for high performance and high reliability. Channels typically use dedicated short-distance connections between computers or between computers and 4Q peripherals.
Features of both channels and networks have been incorporated into a new network standard known as "Fibre Channel". Fibre Channel systems combine the speed and reliability of channels with the flexibility and connectivity of 45 networks. Fibre Channel products currently can run at very high data rates, such as 266 or 1062 Mbps. These speeds are sufficient to handle quite demanding applications such as uncompressed, full motion, high-quality video.
There are generally three ways to deploy Fibre Channel: 50 simple point-to-point connections; arbitrated loops; and switched fabrics. The simplest topology is the point-to-point configuration, which simply connects any two Fibre Channel systems directly. Arbitrated loops are Fibre Channel ring connections that provide shared access to bandwidth via 55 arbitration. Switched Fibre Channel networks, called "fabrics", yield the highest performance by leveraging the benefits of cross-point switching.
The Fibre Channel fabric works something like a traditional phone system. The fabric can connect varied devices 60 such as work stations, PCs, servers, routers, mainframes, and storage devices that have Fibre Channel interface ports. Each such device can have an origination port that "calls" the fabric by entering the address of a destination port in a frame header. The Fibre Channel specification defines the 65 structure of this frame. (This frame structure raises data transfer issues that will be discussed below and addressed by
the present invention). The Fibre Channel fabric does all the work of setting up the desired connection, hence the frame originator does not need to be concerned with complex routing algorithms. There are no complicated permanent virtual circuits (PVCs) to set up. Fibre Channel fabrics can handle more than 16 million addresses, and so are capable of accommodating very large networks. The fabric can be enlarged by simply adding ports. The aggregate data rate of a fully configured Fibre Channel network can be in the tera-bit-per-second range.
Each of the three basic types of Fibre Channel connections are shown in FIG. 1, which shows a number of ways of using Fibre Channel technology. In particular, point-topoint connections 10 are shown connecting mainframes to each other. A Fibre Channel arbitrated loop 11 is shown connecting disk storage units. A Fibre Channel switch fabric 12 connects work stations 13, mainframes 14, servers 15, disk drives 16 and local area networks (LANs) 17. The LANs include, for example, Ethernet, Token Ring and FDDI networks.
An ANSI specification (X3.230-1994) defines the Fibre Channel network. The specification distributes Fibre Channel functions among five layers. As shown in FIG. 2, the five functional layers of the Fibre Channel are: FC-0—the physical media layer; FC-1—the coding and decoding layer; FC-2—the actual transport mechanism, including the framing protocol and flow control between nodes; FC-3—the common services layer; and FC-4—the upper layer protocol.
While the Fibre Channel operates at relatively high speed, it would be desirable to increase speeds further to meet the needs of faster processors. One way to do this would be to eliminate, or reduce, delays that occur at interface points. One such delay occurs during the transfer of a frame from the FC-1 layer to the FC-2 layer. At this interface, devices linked by a Fibre Channel data link receive Fibre Channel frames serially. A protocol engine receives these frames and processes them at the next layer, the FC-2 layer shown in FIG. 2. The functions of the protocol engine includes validating each frame; queuing up DMA operations to transfer each frame to the host; and building transmit frames.
The high bit speeds of the Fibre Channel data link places extreme demands on the protocol engine. Hence, some protocol engines can only operate in half-duplex mode, which means that the protocol engine can process data in only one direction at a time. This significantly slows down the speed of the data transfer since either the transmit or the receive task must wait while the other task is performed.
Full-duplex protocol engines can process both received and transmitted frames simultaneously. Hence full-duplex protocol engines significantly improve data throughput. However, in full-duplex protocol engines, usually two microprocessors, each with local RAM, are required to respectively handle transmit and receive operations. The use of dual microprocessors for these functions greatly increases the cost of the protocol engine.
Conventional approaches to handling frames generally rely on the involvement of a host CPU on a frame-by-frame basis. For example, validation of received frames and setting up direct memory access (DMA) operations and acknowledgments typically involve the host CPU, which limits frame transmission and reception rates and prevents the host CPU from performing other tasks. Further, a host CPU with software protocol "stacks" cannot keep up with fast networks such as Fiber Channel.
In view of the foregoing, objects of the invention include: increasing data transfer processing speeds in high speed
networks such as the Fibre Channel network; providing a technique that can speed up a protocol engine's processing of data frames; providing a protocol engine that can perform high speed full duplex processing of data without involving the host CPU on a frame-by-frame basis; minimizing data 5 traffic between a protocol engine and a host CPU and system memory; and generally offloading protocol processing from a host CPU.
SUMMARY OF THE INVENTION 10
The invention is directed to the processing and transferring of frames of data in a computer data link. The invention is a full-duplex communication processor that uses dual micro-coded engines and specialized hardware to build transmit frames, validate receive frames, and set up host 15 DMA operations without involving a host CPU and without one or more resident microprocessors. A preferred embodiment of the invention uses independent dedicated transmit and receive protocol processors. These independent processors communicate with each other using a transfer ready 20 queue. A context manager provides context information that is used by the receive processor to validate received frames and by the transmit processor to build transmit frame headers.
More particularly, a preferred embodiment of the invention: 1) implements a full-duplex communication processor with independent transmit and receive processors that communicates directly to the host driver software through host memory resident "command", "unsolicited data", and
"response" rings; 2) establishes communication between the dual processors to allow the receive processor to queue work for the transmit processor, which allows a remote device send a frame to the receive processor that will "wake-up" the transmit processor to send data to the remote device without involving the host CPU; and 3) establishes an interlocked information table that allows the transmit and receive processors to operate on the same Input/Output (I/O) command.
In a preferred embodiment, the data channel is a Fibre Channel data link and the full-duplex communication pro- 4Q cessor is configured to process FC-2 protocol Fibre Channel frames.
The details of the preferred embodiment of the present invention are set forth in the accompanying drawings and the description below. Once the details of the invention are 45 known, numerous additional innovations and changes will become obvious to one skilled in the art.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a prior art complex computer 50 network utilizing Fibre Channel technology.
FIG. 2 is a diagram of the five functional layers of the prior art Fibre Channel standard.
FIG. 3 is a simplified block diagram of a communication processing system in accordance with a preferred embodi- 55 ment of the invention.
FIG. 4 is a diagram of a typical prior art Fibre Channel frame of data.
FIG. 5 is a simplified block diagram of a full-duplex g0 communication processor in accordance with a preferred embodiment of the invention.
FIG. 6 is a diagram of an Exchange Context Resource Index (XRI) in accordance with a preferred embodiment of the invention. 65
Like reference numbers and designations in the various drawings refer to like elements.
DETAILED DESCRIPTION OF THE
The invention includes a full-duplex communication processor that improves frame transmission and frame reception rates in high speed data links such as the Fibre Channel. By using independent transmit and receive microcoded engines communicating directly to host driver software, full-duplex network communication is accomplished without involving the host CPU.
FIG. 3 shows a Fibre Channel communication system 20 utilizing the full-duplex communication processor 22 in accordance with a preferred embodiment of the invention. Serial data is received along a Fibre Channel data link 24. Frames generally will comprise three portions, a preamble, a data or "payload" portion, and a trailer portion. In a Fibre Channel data link, for example, the Fibre Channel frame consists of a start of frame (SOF) word (four bytes); a data portion comprising a frame header (six bytes), between zero and 2112 payload bytes, and a cyclical redundancy check (CRC) word (4 bytes); and an end of frame (EOF) word (4 bytes). The frame header is used to control link applications, control device protocol transfers, and detect missing or out of order frames. The CRC word indicates whether there is a problem in the transmission, such as a data corruption, or whether some part of the frame was dropped during transmission.
Frames received from the Fibre Channel data link 24 are processed by an NL port 36 which decodes and parallelizes the incoming serial data into words. The NL port 36 assembles the words into frames. The NL port 36 also checks the CRC word for each frame received and adds a resulting "good-bad" CRC status indicator to other status information bits within an EOF status word that is generated from the EOF word. The NL port 36 then writes the frames into a receive frame FIFO buffer 28. Further details of a preferred FIFO buffer module 28 are described in co-pending patent application entitled "RECEIVE FRAME FIFO WITH END OF FRAME BYPASS", Ser. No. 08/937, 065 filed on Sep. 24, 1997, and assigned to the same assignee of the present invention, the disclosure of which is incorporated by reference.
Fibre Channel frames are then received by the full-duplex communication processor 22, also referred to as a protocol engine. Several functions are performed by the full duplex communication processor 22, including: 1) queuing up a host command to write the data in a received frame into host memory through direct memory access (DMA); 2) validating the frame header to ensure that the frame is the next logical frame that should be received; 3) determining whether the frame is defective or not; and 4) generating transmit frames in response to a received frame or hostgenerated transmit command.
Unlike conventional protocol engines, the full-duplex communication processor 22 does not include a microprocessor. Instead, dual microcoded engines are employed in order to separate the protocol engine receive tasks from the protocol engine transmit tasks. In particular, the full-duplex communication processor 22 includes a receive protocol engine 30 and a transmit protocol engine 32. These protocol engines communicate to each other through a transfer ready queue 60. The receive protocol engine 30 validates the receive frame headers received from the receive frame buffer 28. The transmit protocol engine 32 builds transmit frames and sends them to the Fibre Channel data link 24 through a transmit FIFO 66 and the NL port 36.
The full duplex communication processor 22 works in conjunction with a host computer 40 that includes host