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DIRECT MEMORY ACCESS CONTROL DEVICE
BACKGROUND OF THE INVENTION
The present invention relates to a computer comprising a central processor, a memory for storing information connected to the processor and to at least one controller for a peripheral unit, and a logic unit for control of the memory. Computers are known wherein one or more peripheral unit controllers can access the information contained in the memory singly and directly withour engaging the central processor; such access is commonly called DMA (direct memory access). According to the DMA operation, the concerned peripheral unit interrupts the addressing operations of the central processor, replacing the processor in accessing the memory. This procedure entails a delay in the execution of the program of the central processor inasmuch as simultaneous requests for access by the peripheral unit controller and the central processor are resolved sequentially.
The object of the present invention is to make this type of operation faster by obviating the serious drawback of the arrest of the central processor during the execution of one or more DMA cycles.
The problem is solved by considering that the information contained in memory can be differentiated as information ofexclusive utility for the central processor and as information of common utility for the central processor and for the peripheral units. It follows therefrom that in those cases in which the central processor uses only its own exclusive information there would not be any interference between the possible needs of the peripheral units and the needs of the central processor.
The invention is therefore characterized by a division. According to the ivention, there is now provided a computer comprising a memory divided into two zones, the first accessible exclusively by the central processor and the second accessible both by the central processor and by the peripheral unit controllers, and by a logic unit for controlling the access cycles and for synchronizing access by a peripheral unit controller to the second memory zone with access by the central processor to the first zone, whereby the two accesses take place simultaneously. More precisely, a request by a peripheral controller is delayed so as to synchronize the beginning of its access cycle with the beginning of an access cycle requested by the central processor and addressed to the first memory zone. A request for access by the central processor addressed to the second memory zone is satisfied only at the end of any possible accesses in progress by the peripheral controllers.
A detailed description of a preferred embodiment of the arrangement according to the invention will now be given with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. I shows the general logic diagram of the computer according to the invention;
FIG. 2 is a flow diagram of the sequence of the various operations;
FIG. 3 shows the circuit details of blocks 8 and 9 contained in FIG. 1;
FIG. 4 (comprising FIGS. 4a. 4b and 4c) shows the possibility of division of the memory into two zones;
FIG. 5 shows the switching action of block 9 of FIG. 1:
FIG. 6 shows the circuit details of blocks 14, 15, 16 and 19 of FIG. 2;
FIG. 7 shows the circuit details of the blocks 20 and 21 of FIG. 1;
FIG. 8 shows the timing of the principal signals concerning the logic circuits described.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The arrangement of FIG. 1 comprises: A central processor 1 hereinafter briefly called “the CPU"; a first memory zone 2 accessed exclusively by the central processor and hereinafter called “the private memory“; a second memory zone 3 with common access and hereinafter called “the DMA memory“; three three-state logic circuits 4, 5 and 6 hereinafter called “tristate circuits" which, according to the logical level of the command signal, behave as short circuits or as open circuits for the communication channels in which they are connected and therefore function as physical switches for the channels; a storage device 7, hereinafter called “latch", which is enabled to receive input data by a logical signal, which data will be permanently present at the output until a fresh enabling signal arrives; two logic circuits 8 and 9 for signalling the type and validity of the addressing; an address channel consisting of a first part 11 called BC and a second part 12 called BT; a bidirectional channel 13, called MT, for the communication of data from or for the memory and connected at two monodirectional channels 24 and 25 called ME and ECD, respectively; a block 10 indicating a plurality of peripheral unit controllers called GOPs; two logic circuits I4 and 20 adapted to allocate the cycles of access to the DMA memory 3 to the CPU I or to the GOPs 10, respectively; a logic circuit 15 adapted to generate beginning-of-cycle timing signals; a logic circuit 16, called “the CPU logic switch", which is adapted to enable selectively the connections of the channels ME, ECD and BC with the channels BT and MT which concern the DMA memory 3; two logic gates 17 and 18; a logic circuit I9 adapted to generate end-of-cycle timing signals; and an oscillating and synchronizing circuit 21.
It is pointed out that in FIGS. I, 3, 4, 5, 6 and 8 all the signals whose names end in a vowel are understood to be active at high logical level, while those ending with the letter “N" are active at low level.
Operation of the arrangement of FIG. I takes place in the following manner.
When the CPU makes a request for access to memory, it emits the signal WBCO. This access by the central processor may concern the private memory 2, in which case it will be called “ALFA access" for short, or it may concern the DMA memory 3, in which case it will be called “BETA access". Access by the CPU I to the private memory 2, i.e. an ALFA access, requires no particular enable signal and is never delayed; a BETA access by the CPU, on the other hand, requires suitable enabling or inhibiting operations at the tristate circuits 4, 5 and 6 and at the latch 7 to be effected. The logic circuit 14 provides for the handling of a BETA access. At the inputs of the circuit I4 there are the following signals:
WBCO indicates a general request for access (writing or reading) by the CPU I;
EXMI specifies whether the request for access is of BETA type;
PRQO indicates that the DMA memory is currently engaged by the GOPs 10;
REQSO indicates that there is a request by the GOPs 10. At the outputs:
PRWBO indicates allocation of the cycle of access to the DMA memory 3 to the CPU 1;
STUCN indicates the presence ofa request for access to the DMA memory 3 by the CPU l.
When the four input signals WBCO, EXMI, PRQO and REQSO indicate that a request for access by the CPU 1 to the DMA memory 3 and that the GOPs 10 are not, at present, accessing the same memory. the circuit 14 activates the output signals PRWBO and STUCN.
The signal STUCN has the function principally of enabling the timing circuit 15 to generate timing signals PEOO and CKOO-40.
The signal PRWBO has three functions. The first is to generate the signal STARO for enabling the DMA memory: the signal STARO is generated by the OR gate 18, which has as input the output of the AND gate 17 and the signal PRCO; the AND gate 17 has the signals CKO0 and PRWBO as input. The second function of the signal PRWBO is to enable the tristate circuit 5. In this way the channel BT 12 is connected to the channel BC ll and the CPU l can address the DMA memory 3. The third function is to comnlllld I1"? l°8l¢ circuit 16. The logic circuit 16 organizes the transmission of the data in both directions between the CPU 1 and the DMA memory 3.
ln addition to the signal PRWBO to which reference has just been made, we have the following signals as input to the circuit 16:
REUCO specifies whether access by the CPU I is for reading or writing in memory;
RED! signals that the data read in the DMA memory 3 is ready on the channel MT 13;
READN signals the end of a cycle of access to the DMA memory 3.
As output we have the signals METSA. STROBN and METSN, which enable the tristate circuit 6, the latch 7 and the tristate circuit 4, respectively.
During a writing operation of the CPU 1 in the DMA memory 3, the tristate circuit 4 remains constantly enabled. During a reading operation, the tristate circuit 6 remains constantly enabled, while the latch 7 is enabled whenever the data in the DMA memory 3 is ready to be read.
when the access cycle is ended. the DMA memory 3 generates the end-of-access signal READN. The endof-access signal READN enables the logic circuit 19 to generate the successive end-ofcycle timing signals MEOCO-4 and the signals MEOCN and DONEN. The signals MEOCN and DONEN indicate the end of the access cycle to the CPU 1 and the GOPS 10, respectively.
So far, the case of access by the CPU 1 to the DMA memory 3 has been seen. It is desired in particular to bring into evidence how this access is always possible if requests for access by the GOPs 10 are not present. since requests of the GOPS 10 have priority over the requests made by the CPU 1.
bet us suppose that one or more GOPs 10 simultaneously make a request for access to the DMA memory 3.
The logical OR of these requests for access is sent as input to the logic circuit Z0 by means of the signal REQOO. The other inputs of the logic circuit 20 are constituted by the following details:
CKOO-40 and MEOCO-4 are suitable beginning-of cycle and end-of-cycle timing signals adapted to condition the logical operations of the circuit;
DORIN is a signal indicating the beginning of an ALFA access by the CPU 1 to the private memory 2. As output we have the following signals:
REQSO indicates that the GOPs I0 have made a request;
PRQO indicates that the access cycle has been allocated to the request made by one of the GOPs 10;
PRCO corresponds to the signal PRQO synchronized with timing signals and principally has the function of enabling the DMA memory 3 through the logical OR gate 18;
ACKOA is the signal which enables the GOPs I0 to address the DMA memory 3 in the event of acceptance of the request.
The circuit 20 has the function of synchronizing access to the DMA memory 3 by the GOPs 10 with an ALFA access by the CPU 1 to the private memory 2. This circuit suitably delays the beginning of the cycle of access by the GOPs 10 so as to superpose the two cycles.
Another feature of the logic circuit 20 is that it synchronizes only the first request REQUOO with the beginning of an access of ALFA type, while following requests are accepted immediately, so that they are met without delays and in a sequential manner. In the most general case an access by the GOPs lll to the memory 3 is therefore a group of several sequential accesses.
The logic circuit 21 comprises a quartz oscillator which generates the synchronism signal OSCI. The signal OSCI is used by the above-described logic circuits I4, 16 and 19. The logic circuit 21 moreover generates the signal DORIN whenever the signal ALFAO indicates the beginning of an access to the private memory 2. Explanation of the circuits 8 and 9 and explanation of those signals of FIG. 1 which have not yet been described will be postponed to the detailed examination to follow.
A brief synthesis of operation will now be given with reference to the flow diagram of FIG. 2. When no request coming from the GOPs 10 is present. a possible request of BETA type by the CPU 1 is followed by access to the DMA memory 3 (blocks 30, 36, 35). On the other hand, when a request by the GOPs 10 (block 30) occurs, it is delayed until the CPU I terminates a possible access of BETA type to the DMA memory 3 (block 31). At this point the GOP 10 can access the DMA memory 3 in synchronism with an access of the CPU 1 to the private memory 2 (blocks 32 and 33).
Access requested by a GOP 10 has priority over a BETA access requested by the CPU 1. If, at the end of an ALFA access by the CPU 1 to the private memory 2. the memory 3 is free, an immediate BETA access will follow. If, on the other hand, the DMA memory 3 is engaged by the GOPs 10, the request (BETA) is stored and allowed only on exhaustion of the access cycles done by GOPs 10 (blocks 34, 37, 38 and 35).
FlG. 3 shows in detail the circuit construction of the blocks 8 and 9 of FIG. 1. The circuit 8 serves to program the capacity and the location of the two zones, called the private memory 2 and the DMA memory 3, which we divided the memory into. The circuit 8 has as input the five most significant bits present on the address channel BC ll of the CPU 1 (see FIG. 1). The output signal EXMI indicates by a high logical level that the address presented on the channel BC ll belongs
5 to the private memory 2, while a low logical level indicates that it belongs to the DMA memory 3. The circuit 8 comprises a comparison circuit 40 adapted to compare the configuration composed of the signals BCll-14 and
BXIS with an equal number of signals C11-15. 5
The output AMIBO indicates by a high or low logical level, respectively, whether the configuration formed by the signals BC11-14 and BXl5 represents a number smaller or greater than the comparison configu
The circuit 41 is simply constituted by eleven movable connectors P1-11. These connectors give the option of connecting or not connecting each of the inputs to the corresponding output. This option is essential for
programming the locations and capacities of the zones 2 15
and 3 of the memory. Referring to the following Table 1 and to FIG. 4, three modes of programming are distinguished.
6 consequence is that the connections of the connectors P1-5 actually made bring the inputs Cl1—l5 of the circuit 40 to low logical level, defining in this way the comparison configuration. Those connections Pl—5 not made (N in Table 1) define a corresponding signal C11-15 of high logical level.
It is explained at this point that BCl1-15 represents a number greater than Cll—15 whenever the address present on the channel BC 11 is a number greater than the configuration C15-C14-C13-C12-C11-1-1-1-1-l-l-l1-1-1-1. ln this case the signal EXMI is at high logical level and thus indicates that the address relates to the private memory 2. In the opposite case (address lower than the foregoing configuration), the signal EXMI is at low logical level and indicates that the address relates to the DMA memory 3 (see FIG. 4a).
Mode B differs from mode A only in the fact that the connection P7 is made instead of the connection P6.
MODE A MODE B MODE C
CONNECTIONS CONNECTIONS CONNECTIONS
Psi I P6-l l P6-1 1
CONNECTIONS C N N c c N N C N C c N N c c N N C
P1-5 ADDRESSES ADDRESSES ADDRESSES
1 2 3» 4 5 FROM TO FROM TO FROM TO
N C c c c 0000 07FF 0800 FFFF 0300 2000
C N C c C 0000 OFFF 1000 FFFF 1000 s000
N N C c c 0000 1'/FF 1x00 FFFF lB00 5000
C C N c C 0000 IFFF 2000 FFFF 2000 s000
N c N c C 0000 27FF 2200 FFFF 2000 2000
C N N c C 0000 ZFFF 3000 FFFF 1000 8000
N N N c C 0000 37FF 3800 FFFF 3800 8000
C C c N C 0000 3FFF 4000 FFFF 4000 3000
N C c N C 0000 41i=F 4800 FFFF 4300 2000
c N c N C 0000 4FFF 5000 FFFF 5000 2000
N N C N C 0000 57FF sson FFFF ssoo s000
c C‘ N N c 0000 SFFF 0000 FFFF 0000 2000
N C N N c 0000 67l’-‘F 0300 FFFF 6800 s000
C N N N C 0000 6FFF 1000 FFFF 1000 #000
N N N N c 0000 77FF 1300 FFFF 1300 0000
C c c c N 0000 7FFF s000 FFFF
N c c C N 0000 87FF 8800 FFFF
C N c c N 0000 SFFF 9000 FFFF
N N c c N 0000 97FF 9800 FFFF
C c N C N 0000 9FFF A000 FFFF
N C N C N 0000 A7FF A800 FFFF
c N N c N 0000 AFFF B000 FFFF
N N N C N 0000 B7FF B800 FFFF
C C C N N 0000 BFFF C000 FFFF
N C C N N 0000 C7FF cson FFFF
C N C N N 0000 CFFF D000 FFFF
N N C N N 0000 D'l'FF D800 FFFF
C C N N N 0000 DFFF E000 FFFF
N c N N N 0000 E7FF E800 Fl’-‘FF
C N N N N 0000 EFFF F000 FFFF
N N N N N 0000 FVFF F800 FFFF
It is to be noted that in Table 1 the connections to be made in positions Pl-11 of the circuit 41 of FIG. 3 are
indicated by a while the connections not to be 55
made are indicated by an “N". For each arrangement of the configurations P1-11 there are given in correspondence therewith the various groups of addresses (in hexadecimal notation) belonging to the DMA memory
3. lt can be observed in particular how the capacity of 60
the DMA memory 3 can be incremented by modules having 2048 (2K) words.
In the first mode, mode A, the connections P6, P9 and P10 are made, while the connections Pl—5 program the
capacity of the DMA memory 3. The connection P6 65
puts EXMI equal to the negated form of AMIBO. The connection P9 puts B X l5= BCl5. The connection P10 is a connection with a constantly low logical level. The
The consequence is that, the other conditions being equal, the signal EXMI always gives an opposite indication to that of mode A. The two memory locations are therefore inverted with respect to the previous case (see FIG. 4b).
ln mode C the connections P7, P8 and P11 are permanently made. The result is that as long as the address presented on the channel BC 11 is less than l~ it has the most significant bit BCl5 at low logical level and the circuit 8 behaves as in case B. In fact, when the bit BCl5 is at low logical level, the output signal EXMI indicates that the address present on the channel BC 11 relates to the private memory 2, in the case where the address is lower than the comparison address. On the other hand, in the case where the