SEMICONDUCTOR DEVICE HAVING HIGH
DIELECTRIC CONSTANT LAYERS OF
DIFFERENT THICKNESSES
This application is based on Japanese patent application 5 NO. 2004-144652, the content of which is incorporated hereinto by reference.
BACKGROUND OF THE INVENTION
10
1. Field of the Invention
The present invention relates to a semiconductor device comprising an N-type metal oxide semiconductor field effect transistor (MOSFET) and a P-type MOSFET both containing high dielectric constant films. 15
2. Description of the Related Art
In recent years, the utilization of a thin film having high dielectric constant called high-k as a component material for semiconductor devices is actively investigated. Typical high-k materials include oxides of elements such as Zr, Hf 20 and the like. The use of such materials for a gate insulating film of a MOSFET reduces a silicon oxide-conversion electrical thickness, even though the physical thickness of the gate insulating film is increased to a certain level, thereby providing physically and structurally stable gate insulating films. 25 Thus, both or either one of an increase of metal oxide semiconductor (MOS) capacity for enhancing MOSFET characteristics and a reduction of a gate leakage current as compared with a conventional case of employing silicon oxide can be achieved. 30
Japanese Laid-open patent publication No. 2002-280,461 discloses a complementary metal oxide semiconductor (CMOS) device including an N-MOSFET and P-MOSFET employing such high-k material. The N-MOSFET and P-MOSFET include a gate insulating film composed of a low 35 dielectric constant film such as silicon oxide and the like, and a high dielectric constant film and a gate electrode composed of polycrystalline silicon. The gate electrode is disposed so as to contact with the high dielectric constant film of the gate insulating film. 40
However, a comprehension is obtained according to the recent study, in which a phenomenon called Fermi level pinning is caused when the gate insulating film is composed of a high-k film and the gate electrode is composed of a polycrystalline silicon (C. Hobbs et al., entitled "Fermi Level Pinning 45 at the Poly Si/Metal Oxide Interface", 2003 Symposium on VLSI Technology Digest of Technical Papers, 4-89114-0356/03). It is considered that Fermi level pinning is caused when an energy level is created on the basis of chemical bonding of silicon with the above-described metal for composing the 50 high-dielectric constant film diffusing through the polycrystalline silicon that composes the gate electrode, in vicinity of an interface on the side of the gate insulating film in the gate electrode.
When the metal composing the high dielectric constant 55 film is diffused in the polycrystalline silicon of the gate electrode of the MOSFET, a depletion layer is created in the gate polycrystalline silicon in vicinity of an interface thereof with the gate insulating film. Sufficient electrical field cannot be applied to the gate insulating film due to an influence of such 60 depletion layer even though a gate voltage is applied, and thus it is difficult to induce enough amount of carrier in the channel region. As a result, a problem is arisen, in which a threshold voltage is increased, and further a fluctuation in the threshold voltage is also increased. 65
Such Fermi level pinning is easy to be occurred in a P-type MOSFET that includes a gate electrode composed of a poly
crystalline silicon containing P-type impurity, in particular in a case of employing Hf and/or Zr for the high dielectric constant film.
In the meantime, high dielectric constant films having same composition and same film thickness are employed for gate insulating films of N-type MOSFET and P-type MOSFET, which respectively constitute internal circuits of LSI in conventional CMOS devices. In such case, a problem is occurred that the gate leakage current generated in the N-type MOSFET is higher than that generated in the P-type MOSFET in the CMOS device. Therefore, the gate leakage current in the N-type MOSFET is focused in view of power consumption design, and a high dielectric constant film having a suitable film thickness, which is capable of sufficiently reducing the gate leakage current to an acceptable level, is deposited.
On the other hand, a threshold voltage for the P-type MOSFET employing a high dielectric constant film containing a specific element such as Hf, Zr and the like is increased to a level that is higher than that for the P-type MOSFET employing silicon oxide for the gate insulating film, for the reason stated above, and is eventually increased to a level that provides a difficult situation in establishing a desired threshold voltage by adjusting density of an impurity in the Si substrate.
SUMMARY OF THE INVENTION
The present inventors have found in the process of examining measures to the above-described problem that a quantity of an increase of the threshold voltage is dependent on the film thickness of the high dielectric constant film. In addition, the present inventors also have found that the reason for causing the above-described problem is not from an increase of MOS capacity caused by the reduction of the thickness of the high dielectric constant film, but from the fact that a quantity of the specific element originally contained in high dielectric constant film diffusing from the high dielectric constant film to the gate electrode is dependent on the film thickness thereof, and thus being attained to invent the present invention.
According to one aspect of the present invention, there is provided a semiconductor device, comprising: an N-type MOSFET including: a semiconductor substrate, a first gate insulating film, formed on the semiconductor substrate, and composed of a first high dielectric constant film containing one ormore element(s) selected from a group consisting of Hf and Zr; and a first gate electrode, disposed on the first gate insulating film to contact with the first high dielectric constant film, and composed of a polycrystalline silicon film; and a P-type MOSFET including: a second gate insulating film, formed on the semiconductor substrate to be juxtaposed to the N-type MOSFET, and composed of a second high dielectric constant film containing one or more element(s) selected from a group consisting of Hf and Zr; and a second gate electrode, disposed on the second gate insulating film to contact with the second high dielectric constant film, and composed of a polycrystalline silicon film, wherein a film thickness of the second high dielectric constant film is less than a film thickness of the first high dielectric constant film.
In the configuration described above, the first high dielectric constant film and the second high dielectric constant film may also be composed of a chemical compound of one or more element(s) selected from a group consisting of Hf and Zr and one or more element(s) selected from a group consisting of Si, O and N.
The disclosure of C. Hobbs et al, entitled "Fermi Level Pinning at the Poly Si/Metal Oxide Interface", 2003 Symposium on VLSI Technology Digest of Technical Papers
describes that Fermi level pinning is caused when a high-k film such as HfD2 and the like is provided so as to contact with a polycrystalline silicon. Such Fermi level pinning is considerably influential to the operation of the P-type MOSFET. In particular, the influence to the P-type MOSFET becomes 5 larger when the P-type MOSFET includes the high dielectric constant film containing Hf such as HfD2 and HfAlO. However, since the second high dielectric constant film in the P-type MOSFET is formed to have thinner film thickness in the present invention, the quantity of the metal, which is 10 originally contained in the second high dielectric constant film and is diffused into the polycrystalline silicon film, is reduced, even though the second high dielectric constant film contacts with the polycrystalline silicon film, and thus the generation of the depletion layer in the polycrystalline silicon 15 can be avoided. This can diminish the influence of Fermi level pinning to the P-type MOSFET. Therefore, the increase of the threshold voltage of the P-type MOSFET can be inhibited and the fluctuation thereof can also be reduced.
In addition, the high dielectric constant film in the N-type 20 MOSFET can be formed to have larger film thickness, and thus the enhancement of the gate leakage current, which is a problem for the N-type MOSFET, can be also inhibited.
The semiconductor devices according to the above-described aspects of the present invention may further has a 25 configuration, in which the first high dielectric constant film and the second high dielectric constant film may contain Hf and Si. In addition, in such case, a content ratio of Hf for the total content of Hf and Si may be equal to or higher than 20 atomic % in the first high dielectric constant film and the 30 second high dielectric constant film. More preferably, the content ratio of Hf for the total content of Hf and Si may be equal to or higher than 30%. The semiconductor devices according to the above-described aspects of the present invention may further have a configuration, in which the first high 35 dielectric constant film and the second high dielectric constant film may be respectively and independently composed of HfSiO or HfAlO, or nitride thereof. In such case, a lower limit of the percentage of Hf over the total content of Hf and Al in HfAlO may be equal to or higher than 20 atomic %. 40 Further, the semiconductor devices may have a configuration, in which the first high dielectric constant film and the second high dielectric constant film are free of Al.
The influence of Fermi level pinning in the P-type MOSFET may be a problem in the above-described cases. On the 45 contrary, since the second high dielectric constant film in the P-type MOSFET is formed to have thinner film thickness in the present invention, this can diminish the influence of Fermi level pinning to the operation of the P-type MOSFET, as described above. 50
The semiconductor devices according to the above-described aspects of the present invention may further have a configuration, in which the first gate insulating film of the N-type MOSFET further includes a silicon oxide film provided between the semiconductor substrate and the first high 55 dielectric constant film, and the second gate insulating film of the P-type MOSFET further includes a silicon oxide film provided between the semiconductor substrate and the second high dielectric constant film. The silicon oxide film may include nitrogen. 60
Diffusion, migration or the like of the metal contained in the first high dielectric constant film and the second high dielectric constant film into the semiconductor substrate can be prevented by providing the silicon oxide films between the semiconductor substrate and the first high dielectric constant 65 film and between the semiconductor substrate and the second high dielectric constant film, respectively.
The semiconductor devices according to the above-described aspects of the present invention may further have a configuration, in which, in the first gate electrode of the N-type MOSFET in the semiconductor device, the polycrystalline silicon film includes an N-type impurity, and in the second gate electrode of the P-type MOSFET, the polycrystalline silicon film includes a P-type impurity.
Fermi level pinning described above is considerably caused when the polycrystalline silicon film containing P-type impurity contacts with the high dielectric constant film. On the contrary, since the second high dielectric constant film in the P-type MOSFET is formed to have thinner film thickness in the present invention, the quantity of the metal, which is originally contained in the second high dielectric constant film and is diffused into the polycrystalline silicon film, is reduced, even though the second high dielectric constant film contacts with the polycrystalline silicon film, and thus the generation of the depletion layer in the polycrystalline silicon can be avoided.
The semiconductor devices according to the above-described aspects of the present invention may further have a configuration, in which a relationship of a film thickness dl of the first high dielectric constant film with a film thickness d2 of the second high dielectric constant film is: dl/d2isl.5. Further, while the upper limit thereof is not particularly limited, the upper limit thereof may be, for example, dl/d2£=3.
The influence of Fermi level pinning can be moderated to reduce the threshold voltage and the increase of the gate leakage current can be inhibited by providing such relationship between the film thickness of the first high dielectric constant film and the film thickness of the second high dielectric constant film. When the first high dielectric constant film is composed of, for example, HfSiNO, the film thickness dl may be equal to or higher than 1.5 nm. Having this configuration, the increase of the gate leakage current in the N-type MOSFET can be inhibited. In addition, the film thickness d2 of the second high dielectric constant film may be equal to or less than 1 nm, for example, and more preferably equal to or less than 0.5 nm. Having such configuration, the influence of Fermi level pinning can be reduced.
The semiconductor devices according to the above-described aspects of the present invention may further have a configuration, in which the N-type MOSFET and the P-type MOSFET compose internal circuits of LSI.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device including an N-type MOSFET and a P-type MOSFET, comprising: forming on an entire surface of a semiconductor substrate a first layer composed of a high dielectric constant material including one or more element(s) selected from a group consisting of Hf and Zr, said semiconductor substrate being provided with a P-well and an N-well that are juxtaposed; covering said first layer on said P-well with a protective film; selectively removing said first layer on said N-well through a mask of said protective film; forming on at least said N-well a second layer composed of a high dielectric constant material including one or more element(s) selected from a group consisting of Hf and Zr; forming a polycrystalline silicon film on said first layer and said second layer; selectively removing said first layer, said second layer and said polycrystalline silicon film to form the layers into a shape of a gate electrode, wherein said second layer is formed in said forming said second layer to provide a total film thickness of said first layer and said second layer on said N-well, which is thinner than a total film thickness of said first layer and said second layer on said P-well.
|
