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INSULATING FILM FORMING METHOD FOR
BACKGROUND OF THE INVENTION
This invention relates to the manufacture of semiconductor devices, and more particularly to an insulating film forming method for semiconductor device interconnection which is suitable for manufacture of highly 10 integrated devices of multilevel interconnection structure, and to an apparatus for carrying out the method.
With the recent trend toward semiconductor devices of higher integration and higher density, the roughness of surface shape of the semiconductor devices has be- 15 come greater, and reliable formation of a number of layers for interconnection on such a surface has come to be required. It is therefore necessary to form an insulating film for insulating the interconnection layers from each other, independently of the rough shape of the 2C) underlying surface and in such a manner that the insulating film will have a planar surface. For planarization of the insulating film, the methods under investigation at present are disclosed in Denki Kagaku (published by the Electrochemical Society of Japan) Vol. 57, No. 4 25 (1989), pp. 281-285, and Semicon NEWS 1989, June, pp. 49-67.
Many planarization methods which employ sputteretching, etchback, reflow or the like have been proposed and studied. 30
For the formation of insulating films between interconnections for a semiconductor device, it is necessary not only to form a planar film but also to avoid influences of the film forming process on the device characteristics, to prevent the formation of voids in the film, to 35 suppress dust generation attendant on the process, and so on. For higher productivity, in addition, the film forming process should not involve a wet treatment, such as use of a coating film, and should enable continuous processing in vacuum. 40
The above-mentioned prior arts have the following drawbacks. The method which uses sputter-etching and enables continuous processing in vacuum has the problems of influencing the device characteristics and generating dust. The methods using a coating film or etching 45 are disadvantageous in that they use a combination of a wet process and a vacuum process. None of the conventional insulating film forming methods for semiconductor device interconnection satisfies the above-mentioned performance requirements for mass-production. 50
A general description of the conventional insulating film formation techniques is found, for example, in Semiconductor World, 1989, November, pp. 78-83.
SUMMARY OF THE INVENTION 55
It is an object of this invention to provide an insulating film forming method for semiconductor device interconnection which overcomes the above-mentioned drawbacks of the prior art and which is suitable for mass-production, and an apparatus for carrying out the 60 method.
In order to attain the above object, this invention provides an insulating film forming method for semiconductor device interconnection comprising: (i) a film forming step which comprises introducing an admixture 65 of a film forming source gas for plasma CVD with an etching gas (reactive gas) comprising a fluorine-containing compound into a processing chamber of a
plasma treatment system, to thereby generate a plasma; heating a substrate on a stage in the processing chamber so as to effect plasma CVD with the film forming source gas, thereby depositing an insulating film on an interconnection pattern of the substrate; and, simultaneously with the deposition of the film, directing gas ions of the fluorine atom containing gas in the reactive gas onto the insulating film by a potential difference developed between the plasma and the stage, so as to gasify a portion of the insulating film through a chemical reaction with the fluorine atom containing gas ions and to effect reactive etching, thereby forming an insulating film free of void on the interconnection pattern of the substrate; and (ii) a film planarization step which comprises cooling the substrate provided with the insulating film on the interconnection pattern; supplying a gas of a material being decomposable by the same reactive gas as used for etching of the insulating film and having a melting point higher than the temperature of the cooled substrate, into the processing chamber, so as to adsorb the gaseous material on the substrate; raising the temperature of the substrate to or above the melting point of the adsorbed material to convert the adsorbed material into a liquid, thereby planarizing the surface of the material; then lowering the temperature of the substrate to or below the melting point to solidify the adsorbed material; and subsequently performing reactive etching by use of the reactive gas and the plasma under such conditions as to equalize the etching rates of the solidified material film and the insulating film therebeneath, whereby the planeness of the surface of the solidified adsorbed material is printed on the surface of the insulating film. The adsorbed gas material can be said to serve as a sacrificing material for planarization by etchback.
When the film forming source gas for forming an insulating film by plasma CVD is admixed with the fluorine-containing etching gas and the plasma is generated to carry out the processing, the film formation from the film forming source gas proceeds with the accompanying reactive ion etching by the etching gas, whereby the film being formed is etched principally in the direction perpendicular to the substrate, and a film is formed in a tapered shape on side walls of the interconnection pattern. The film formed on the side surfaces of the pattern has a tapered shape broader at the top portion of an opening. Therefore, the growth of the film on the side surfaces of the pattern, on both sides of an opening, proceeds gradually from the bottom portion of the opening, so that no void is generated in the film thus formed.
In addition, the conversion of the gas material adsorbed on the surface of the substrate into a liquid renders the surface of the material planar, regardless of the surface shape of the substrate, and cooling the liquid material to or below the melting point thereof results in that the surface of the substrate is covered by a planar, solidified film of the material When etching is subsequently carried out under such conditions as to equalize the etching rates of the thus solidified film and the formed insulating film, the etching proceeds in accordance with the surface shape of the solidified film, irrespective of the rough surface shape of the insulating film, so that the insulating film surface becomes planar.
In the above-mentioned step (i), i.e. the film forming step, the insulating film is formed through deposition and, simultaneously, a portion of the insulating film thus
formed is etched, with the etching rate controlled to within the range from 1/5 to 4/5 times the deposition rate. When the etching rate is below the range, void is produced in the insulating film obtained. When the etching rate is above the range, on the other hand, the 5 combination of deposition and etching results in a lowered formation rate of the insulating film. Both of these cases, with the etching rate outside the above-mentioned range, thus lead to undesirable results. The control of the etching rate of the insulating film to within 10 the range from 1/5 to 4/5 times the deposition rate can be achieved by regulating the flow rate of the etching gas introduced into the plasma treatment system to within the range from 1/20 to 4/5 times the flow rate of the film forming source gas, on a volume basis. Besides, 15 the total gas pressure inside the plasma treatment system may be 0.1 to 103 Pa, as usual.
The film formation rate can be controlled by regulating the ratio of the flow rate of the etching gas to the flow rate of the film forming source gas within the 20 above-mentioned range. The film formation rate can be increased by reducing the flow rate of the etching gas, and can be lowered by increasing the etching gas flow rate. The film formation rate can be increased also by increasing the total gas flow rate, without varying the 25 above-mentioned flow rate ratio. Variations in the deposition rate or etching rate of the insulating film with variations in other conditions, such as high-frequency power, are fundamentally the same as in the conventional plasma CVD or plasma etching. 30
In the above-mentioned step (ii), i.e. the film penalization step, it is generally preferable to set the pressure of the material gas introduced into the plasma treatment system in the range from 0.1 to 103 Pa, in accordance with the etching gas pressure in the subsequent etch- 35 pack step of 0.1 to 103 Pa; however, a material gas pressure above the range may also be employed.
The equalization of the etching rate of the solidified adsorbed gas material (sacrificing material) to the etching rate of the insulating film therebeneath can be easily 40 achieved by regulating the high-frequency power for the plasma treatment system, but other methods may also be employed for the equalization. In general, an increase in the high-frequency power results in that the etching rate of the adsorbed gas material and the etch- 45 ing rate of the insulating film are increased simultaneously, but with different gradients of increase. Ordinarily, the gradient of increase in etching rate, with increasing input power, is greater for the insulating film than for the adsorbed material film. This is illustrated by 50 FIG. 5, in which line 101 represents the variation in the etching rate with varying input power, of the insulating film, and line 102 represents that of the solidified adsorbed gas material. As seen from FIG. 5, there is a high-frequency power value Peq at which the two etch- 55 ing rates are equal. It is therefore possible to achieve the film planarization, by adjusting the input power to Peq.
As mentioned above, this invention can be embodied most effectively by a combination of the film forming step of the invention with the film planarization step of the invention. However, a combination of the film forming step of this invention (the above-mentioned step (i)) with a conventional film planarization step or a combination of a conventional film forming step with the film planarization step of this invention (the abovementioned step (ii)) can also be used, to give better results than those obtained by use of the conventional methods of forming an insulating film for interconnec
tion. The conventional film planarization steps include, for example, a coating film method (SOG method), a sputter-etching method, an etchback method employing a resist film, etc., whereas the conventional film forming steps include, for example, a CVD method using a TEOS (Tetra Ethyl Ortho-Silicate) gas, etc.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic sectional view of an insulating film forming apparatus for semiconductor device interconnection, particularly for forming an insulating film, according to one embodiment of this invention;
FIG. 2 is a schematic sectional view of an insulating film forming apparatus for semiconductor device interconnection, particularly for planarizing an insulating film, according to another embodiment of this invention;
FIGS. 3a, 3b and 3c are sectional views illustrating an insulating film forming process by use of the apparatus shown in FIG. 1;
FIGS. 4a, 4b, 4c and 4d are sectional views illustrating an insulating film planarizing process by use of the apparatus shown in FIG. 2; and
FIG. 5 is a graph showing the relationship between a high-frequency (RF) power input to a plasma treatment system and the etching rate in plasma etching.
DETAILED DESCRIPTION OF THE
Some preferred embodiments of this invention will now be described below with reference to FIGS. 1,2,3 and 4.
FIG. 1 shows the construction of an apparatus for forming a void-free insulating film on a rough-surfaced interconnection pattern, particularly the construction of a processing chamber of the apparatus, which will be explained below.
The processing chamber 1 has an upper electrode 2 and a lower electrode 3 incorporated therein. The upper electrode 2 is insulated from the processing chamber 1 by a ceramic plate 4, and connected with an RF power supply 5 of a high frequency of 13.56 MHz. A gas flow controller 6 and a gas supply pipe 7 are provided so that an ... gas, an 62 gas and a CF4 gas can be supplied therethrough. The gas is supplied in a shower-like form into the processing chamber 1 through a small gas supply port 8 provided in the upper electrode 2. A semiconductor wafer 9 provided with an interconnection pattern on its surface is placed on the lower electrode 3. A heater 10 is incorporated in the lower electrode 3, and temperature is controlled by a heater power supply controller 11. The lower electrode 3 is insulated from a base 12 by an insulating block 13, thereby being insulated from the processing chamber 1, and is earthed through by a variable resistor 14.
An exhaust pipe 15 is connected to the processing chamber 1 so that the pressure inside the processing chamber 1 can be controlled to a preset value by an exhaust device, not shown.
On the lower side of the processing chamber 1 is provided a transferring chamber 16, in which a mechanism (not shown) is provided for driving the base 12 upward and downward.
With the base 12 pushed up, the base 12 and the processing chamber 1 are so engaged that the processing chamber 1 is hermetically sealed. The wafer 9 is trans5
ferred by a transferring mechanism (not shown) in the transferring chamber 16, in the condition where the base 12 is lowered.
For other aspects of the above-mentioned insulating film forming apparatus shown in FIG. 1, there" can be 5 used the conventional techniques of parallel plate plasma treatment system.
Now, the formation of an insulating film for interconnection by use of the apparatus shown in FIG. 1 will be explained with reference to FIGS. 1, 3a, 3b and 3c. 10
The wafer 9 is fed into the processing chamber 1, and the base 12 is pushed up to hermetically seal the processing chamber 1. The gas flow controller 6 is operated to mix the ... O2 and CF4 gases together and supply the mixed gas through the gas supply port 8 in a 15 shower-like form. The wafer 9 is heated on the lower electrode 3 to a temperature of 300° to 400" C, the pressure inside the processing chamber 1 is controlled to a preset value, and a high-frequency voltage is impressed on the upper electrode 2 from the high-fre- 20 quency power supply 5, thereby generating a plasma 60 in the processing chamber
The flow rates of the ... O2 and CF4 gases were controlled to 100 cc/min, 0-800 cc/min and 20-400 cc/min, respectively, at 1 atm. Where the flow 25 rate of the O2 gas was zero, the flow rate of the CF4 gas was controlled to 20 cc/min, whereas when the O2 gas flow rate was high, the CF4 flow rate was also made high. The total gas pressure inside the processing chamber 1 was regulated to 10 Pa. The high-frequency volt- 30 age applied was 100 to 500 V, with the frequency being 13.56 MHz. Generally, the frequency may be in the range from 400 kHz to 30 MHz.
The plasma 60 decomposes the ... gas, and the resulting silicon (Si) component reacts with the O2 35 gas to form a silicon oxide film (SiC>2 film) 51 on an interconnection film 50 provided on the wafer 9 being heated by the heater 10. Simultaneously, the carbon (C) and hydrogen (H) arising from the decomposition are reaction with the Chgas. On the other hand, the CF4gas 40 supplied in the mixed, shower-like form through the gas supply port 8 is decomposed, in the plasma 60, to CF3+ and F radicals. The applied high-frequency voltage generates a potential difference in a sheath between the upper electrode 2 and the plasma 60. Other potential 45 differences due to the applied high-frequency voltage are also generated between the plasma 60 and the inner wall 61 of the processing chamber 1 and between the plasma 60 and the lower electrode 3.
Because the plasma treatment apparatus is of the 50 anode coupling type in which the RF power supply 5 is connected to the upper electrode 2, as shown in FIG. 1, the potential difference generated between the upper electrode 2 and the plasma 60 is greater than the potential differences generated between the inner wall 61 of 55 the processing chamber 1 and the plasma 60 and between the lower electrode 3 and the plasma 60. The CF3+ ions are accelerated by the potential difference between the sheaths, and are directed onto the electrode 3 or the wafer 9. The silicon oxide film (Si02 film) 51 60 formed on the wafer 9 reacts with the CF3+ ions directed thereto with acceleration, forming an SiF4 gas and a CO2 gas, which are exhausted through the exhaust pipe 15. Thus, etching proceeds.
In this case, the CF3+ ions are accelerated and so 65 directed as to be perpendicularly incident on the wafer 9. Therefore, even portions and overhanging portions of the silicon oxide film (S1O2 film) 51 are etched pre
dominantly, without progressive etching of side surfaces of stepped portions of the film 51. In addition, a sputtering effect of the CF3+ ions causes a preferential etching of film surfaces lying at an angle of about 45" relative to the perpendicular direction, whereby the progress of etching is assisted. The deposition rate of the oxide silicon film was about 600 nm/min, and the etching rate was 300 to 400 nm/min.
In this manner, the silicon oxide film (Si02 film) 51 is formed by the reactions between the decomposed gases of the ... gas and the O2 gas, while the overhanging portions and the slant surfaces with an inclination angle of about 45°, of the silicon oxide film thus formed, are preferentially etched As a result, the silicon oxide film 51 thus obtained has a tapered shape as shown in FIG. 3a, with no void formation in the silicon oxide film 51. In other words, this silicon oxide film forming process is free of the possibility that a film may be deposited in an overhanging form on the upper side of the interconnection film 50 and the overhanging portions on both sides may make contact with each other to form void in the deposited film. Therefore, a silicon oxide film free of voids can be formed, as shown in FIG. 3b, by the process. The processing is further continued in the processing chamber 1 to form the silicon oxide film until the shape shown in FIG. 3c is obtained, upon which the processing is completed.
In this method, the conventional etching of a silicon oxide film by sputter-etching with Ar+ ions is not employed but, instead, a portion of the silicon oxide film is gasified by chemical reactions and exhausted. Therefore, deposition of sputtered silicon oxide films on the inner wall 61 of the processing chamber 1 or the like with the resultant formation of dust can be prevented, and the silicon oxide film 51 of high quality can be formed on the interconnection film 50.
Besides, ... SiF4 and SiH4 gases and the like, other than the gas used in the above embodiment, can also be used as the film forming source gas.
Further, the etching gas may be any fluorine-containing gas, such as C4F8, C3F8 and CHF3.
In this embodiment, the potential difference between the upper electrode 2 and the plasma 60 is greater than the potential differences between the inner wall 61 of the processing chamber 1 and the plasma 60 and between 10 the lower electrode 3 and the plasma 60, as has been described above. Because the rate of etching of the silicon oxide film 51 by the CF3+ ions is proportional to this accelerating voltage, the etching rate of the film on the surface of the upper electrode 2 in this embodiment is higher than the etching rate of the film on the surface of the wafer 9, and is 600 to 800 nm/min. The deposition rate of the silicon oxide film 51 on the upper electrode 2 and the deposition rate of the film 51 on the lower electrode 3 are equal. It is therefore possible to form the silicon oxide film 51 only on the wafer without deposition of the film on the upper electrode 2, by controlling the etching rate of the film on the upper electrode 2 to a value equal to or higher than the deposition rate of the film on the upper electrode 2. Accordingly, it is possible to prevent the generation of dust arising from exfoliation of a deposited film on the upper electrode 2, and to realize formation of a silicon oxide film of high quality.
Furthermore, when the impedance to a high-frequency current flowing through the lower electrode 3 is raised by the variable resistor 14 to reduce the highfrequency current flowing through the lower electrode 3, as in this embodiment, the potential difference be