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SWITCHING ARRANGEMENT AND
METHOD WITH SEPARATED OUTPUT
This application claims the benefit of European Patent 5 Application Number 01104850.1 filed on Feb. 28, 2001.
The invention relates to a switching arrangement for pack- i o ets of data, with several input ports and several output ports and which is determined for the transportation of incoming packets to one or more designated of the output ports and from there to a subsequent device. More particularly it relates to a switching arrangement and method wherein for each 15 input port a set of output buffers is arranged, each set comprising an output buffer for each output port. As data packets, particularly ATM cells or also Ethernet frames can be accepted.
DESCRIPTION OF PRIOR ART
Fast switching of information, be it samples of analog signals or alphanumeric data, is an important task in a communication network. The network nodes in which lines or 25 transmission links from various directions are interconnected for exchanging information between them are often the cause of delay in the transmission. If much traffic is concentrated in a node, and if in particular most of the traffic passes through only few of the links, increased delays or even loss of infor- 30 mation are often encountered. It is therefore desirable to have switching nodes which allow fast routing.
In EP 312628 is described a switching apparatus for interconnecting a plurality of incoming and outgoing transmission links of a communication network, or for exchanging data 35 between incoming and outgoing computer- and workstation connection links. Furthermore, known packet formats are described.
An overview over prior art switching technology is given on the Internet page www.zurich.ibm.com/Technology/ 40 ATM/S WOCPWP, wherein an introduction into the PRIZMA Chip is illustrated. Another source for information about this topic is the publication "A flexible shared-buffer switch for ATM at Gbit/s rates" by W. E. Denzel, A. P. J. Engbersen, I. Iliadis in Computer Networks and ISDN Systems, (0169- 45 7552/94), Elsevier Science B. V., Vol. 27, No. 4, pp. 611 -624.
The PRIZMA chip comprises a shared common output buffer has 16 input ports and 16 output ports which provide a port speed of300-400 Mbit/s. The switch's principle is first to route incoming packets through a fully parallel I/O routing 50 tree and then to queue the routed packets in the output buffer. In addition to this, the chip uses a separation between data (payload) and control (header) flow. Only the payloads are stored in a dynamically shared output buffering storage. With this architecture, head-of-the-line-queuing is avoided. The 55 PRIZMA chip has a scalable architecture and hence offers multiple expansion capabilities with which the port speed, the number of ports and the data throughput can be increased. These expansions can be realized based on a modular use of the PRIZMA. Also single-stage or multi-stage switch fabrics 60 can be constructed in a modular way.
The PRIZMA chip is especially suited for broadband telecommunications, based on ATM, i.e. the Asynchronous Transfer Mode. However, the concept is not restricted to ATM-oriented architectural environments. ATM is based on 65 short, fixed-length packets, often called cells and is supposed to be applied as the integrated switching and transmission
standard for the future public Broadband Integrated Services Digital Network (BISDN). PRIA's topology and queuing arrangement for contention resolution employs a high degree of parallelism. The routing function is performed in a distributed way at the hardware level, referred to as self-routing. ATM packets are classified into several packet types, particularly packet types with different payload sizes, and the PRIZMA chip is dedicated to handle packets with a payload up to 64 bytes. However, also packet payloads with 12,16,32 or 48 bytes are often to be transported.
The bandwidth through the shared memory of an outputqueued switch must equal N times the individual port speed, which poses significant implementation concerns at high line rates. Because of this, input-queued switches have gained popularity in recent years. The performance limitations of FIFO-queued crossbar-based switches have been largely overcome by applying techniques such as virtual output queuing (VOQ), combined with centralized scheduling to achieve good throughput. VOQ entails the sorting of incoming packets at the input side based on the packet's destination output.
Packet switches that rely solely on output queuing are not well scalable to high data rates because of the high memory bandwidth requirement. Implementations that use a high degree of parallelism can achieve the desired bandwidth, but limit the amount of memory that can be integrated on a single chip, thus potentially leading to high packet loss rates and highly traffic-dependent performance.
OBJECTS OF THE INVENTION
It is an advantage of the invention according to the claims that the switching arrangement is less expensive than other switching arrangement with comparable performance because the output router function is substituted by a multiplication of output buffer space which is much cheaper than the space needed for an output router. Output routers need an extraordinary amount of wiring which is not necessary for memory. Furthermore the logic circuitry for processing the data packets becomes less complex which facilitates circuit design.
A switch input queue can be arranged for queuing therein the data packets arriving at the input port. Such a queue has the advantage that it can buffer the data packets whereby for each data packet only one copy is stored instead of multiple copies in the output buffers.
An address manager can be arranged for managing the use of the addresses of the output buffer, and an output queue router can be used for entering the addresses at which the data packets are stored in the output buffer, into the output queues.
A bypass for leading the payload directly from the input port to its multiplexer has the advantage that the data packets can be processed without using the output buffers, an address and the output queues. This saves time, reduces system usage and the risk of backpressure.
A congestion detector can be used for allowing the data packet to be led via the corresponding bypass when the corresponding multiplexer is able to multiplex the data packet to its output port. This provides a simple solution for deciding whether a data packet can be transferred directly to the output port.
The output queues can provide in total more queuing places for the addresses than the corresponding output buffer has addresses. When the output queues have more queuing places than the output buffer has addresses, a non-equal distribution between the various input queues can be handled without losing data packets. A total unequal distribution could be
buffered completely if each output queue has the number of queuing places equal to the number of addresses in the corresponding output buffer.
An input buffer with at least as many input queues as the switching arrangement has output ports, whereby the input 5 queues serve for sorting the arriving data packets according to their dedicated at least one output port reduces the risk of head-of-the-line blocking.
An input controller for each input port, serving for controlling the order of multiplexing the data packets from the input 10 queues to the switching device, is advantageous since it provides autonomous control for the corresponding input queues, which reduces the control complexity for the input queueing mechanism.
An output-queue threshold comparator can be used for 15 signaling to the input buffers if a threshold value of occupied places in the total of all output queues pertaining to one common output port is exceeded. Such a common threshold comparator uniting the filling degrees of all output queues pertaining to one and the same output port is advantageous 20 because, thereby the true traffic heading for this one output port is measured and used to create a feedback onto the input queues that leads to an effective traffic control in case of congestion.
Upon a signal from the output-queue threshold comparator 25 that the threshold value of occupied places in the total of all output queues pertaining to the same output port is exceeded, only the input queue which corresponds to the same output port should be prevented from delivering its data packets to the same output port. Distributing thereby the feedback from 30 the threshold comparator to the input queues in a selective way, namely only to those input queues that hold data packets for the corresponding output port where the congestion has occurred, brings the advantage that not an unneccessary blocking effect is introduced by backpressure. Thereby the 35 head-of-the-line blocking effect is reduced also in case of congestion.
An output buffer backpressure generator can be provided for signaling to the input buffer corresponding to the output buffer that a threshold value of occupied addresses in the 40 output buffer is exceeded. Such output buffer backpressure generation is practical in that the risk of loss of data packets due to the output buffer being full is reduced.
For a multicast data packet the address thereof can be entered in each of the output queues for the output ports which 45 this multicast data packet is intended to reach and the address is then only released by the address manager for use for another data packet, when all entries of the multicast data packet have been used for delivering the multicast data packet to its designated output ports. Multicast data packets can be 50 hence handled by storing the payload only once in the output buffer and entering the address thereof in the output queue of every output port, this data packet is heading for. A counter can be used that is decremented each time the address is read out from the output queue and which when reaching zero, 55 enables the release of the address for further use.
For data packets with different handling-priorities, for each class of priority and for each output port a separate input queue can be provided in the input buffer. Different input queues for handling different priorities allow data packets 60 with higher priority to pass by those with lower priority.
A demultiplexer can be used for making for each of the arriving data packets an entry into those of the input queues, which are identified in the packet destination information of the corresponding data packet, whereby each input controller 65 is designed to allow simultaneous transmission of those data packets whose entries are located in different of the input
queues and who have identical payload. This provides a way of handling multiplex data packets by putting copies for each dedicated output port into the corresponding input queue and multiplexing those copies at the same time, if the output port status allows this. Each entry may comprise at least the payload of the corresponding data packet or a pointer to a memory cell wherein at least the payload of the corresponding data packet is stored, the memory cell preferably being located in a common input buffer. Hence also in the input buffer, a system is feasible that only queues the headers and stores the payloads in a separate memory section, also referred to as common input buffer. In such a case, the payload of a multicast data packet needs only be stored once which saves memory space.
The demultiplexer can be designed to make several entries in the input queues and only one entry of the payload thereof in a memory cell.
SUMMARY OF THE INVENTION
The invention proposes a switching arrangement for transporting data packets from input ports of a switching device to output ports thereof. The data packets comprise a payload. There is also associated data packet destination information. The switching device is able to route the arriving data packets according to the data packet destination information to at least one dedicated of the output ports.
The switching arrangement comprises for each set of input ports in the switching device a set of output buffers. Such a set of input ports may comprise one or several input ports. This set of output buffers comprises for each set of output ports an output buffer for storing at least the payload of each data packet arriving at the corresponding input port, belonging to the set of input ports, at an address in at least those of the output buffers which pertain to the same set of output buffers, and which belong to the dedicated output ports. A set of output ports may comprise one or several output ports. For at least one of the output buffers a set of output queues is arranged which comprises for each output port an output queue, for storing therein, sorted according to the data packet destination information, the address of each payload stored in the corresponding output buffer. For the output queues which pertain to the same output port an arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the stored payloads from the output buffers to the output ports.
In this switching arrangement the data packets are not only stored in an output buffer and afterwards routed to the designated output port, but the data packet is stored in an output buffer already assigned to the correct output port. Thereafter no routing is anymore necessary. The only action after having stored the data packets is to select which of the data packets may be allowed to be forwarded to its output port. This task is performed by the arbiter and the multiplexer. The storing of the data packets in the output buffers may be done in several different manners.
On one hand there may be arranged only one address management and output queue set for all output buffers belonging to the same input port. This facilitates the control and reduces the space required therefor.
On the other hand each output buffer can be assigned to an own set of output queues with a separate address space. The additional circuitry leads to an enlarged address space which increases the throughput capacity for burst traffic of data packets.
A bypass for leading the data packets directly from the input ports to the output ports can be arranged together with a mechanism that signals to the bypass that it can be used. This bypass decreases the complexity of handling data packets in low-traffic conditions. 5
BRIEF DESCRIPTION OF THE DRAWINGS
Examples of the invention are depicted in the drawings and described in detail below by way of example. It is shown in 10
FIG. 1 an input-buffered switch arrangement with a set of output buffers per input port,
FIG. 2 an input-buffered switch arrangement with a set of output buffers per input port and with a set of used output queues per output buffer, 15
FIG. 3 an output buffer with output queues, arbiter, multiplexer and a bypass,
FIG. 4 an input-buffered switch arrangement with the input ports and output ports being pairwise grouped in sets.
All the figures are for sake of clarity not shown in real 20 dimensions, nor are the relations between the dimensions shown in a realistic scale.
DETAILED DESCRIPTION OF THE INVENTION
In the following, the various exemplary embodiments of the invention are described.
In FIG. 1 an input-buffered switching arrangement for handling data packets is shown. The arrangement comprises a switching device 10 with a number N of input ports 20 and a 30 number N of output ports 30. The number N is here 32. At each input port 20, labelled with "IP", an input buffer 11, designated also with "IB", is arranged. Each input buffer 11 comprises an input controller 25, designated also with "Ctrl", which is itself connected to the switching device 10. The 35 purpose is to lead the data packets, which arrive at the input buffers 11 via communication lines 50, and which are supposed to arrive at one or more of the output ports 30, to these output ports 3 0. From the output ports 3 0, the data packets can be delivered to subsequent devices, be it further switching 40 devices or receiving devices, etc.
The data packets are here divided up into a packet header section and a packet payload section. In the packet header section, data packet destination information in contained, telling to which of the output ports 30 the respective data 45 packet is to be delivered. Such data packet destination information may also be available from another source such that the data packet need not comprise the data packet destination information. There exist two types of data packets with respect to their data packet destination information: unicast 50 data packets and multicast data packets. A unicast data packet is a data packet that has only one of the output ports 30 as its destination. In contrast hereto, a multicast data packet is destined for more than one of the output ports 30. Hence, by definition, a multicast data packet is a data packet whose 55 payload is destined for several output ports 30. In the packet payload section of the data packet any data that is to be delivered to a destination can be contained.
Input Buffer 60
The input buffers 11 are each split up into a multitude of input queues 12, whereby each input buffer 11 has exactly one such input queue 12 for each output port 30. So each input buffer 11 comprises here N input queues 12. Each of these input queues 12 in one input buffer 11 serves for storing 65 therein the arriving data packets for one dedicated output port 30. So the arriving data packets are sorted in each input buffer
11 according to their destination output port 30. Hence, if a unicast data packet heading for a certain output port 30 is blocked due to this output port 30 being busy, the only data packets that are blocked by this head-of-the-line-blocking unicast data packet are data packets heading for the same output port 30, while data packets heading for another output port 30 can be handled independently and be forwarded to the switching device 10 when the path towards their destination output port 30 is unoccupied. This sorting per destination is also referred to as Virtual Output Queuing, short VOQ. The multitude of the input queues 12 together is also referred to as VOQ.
For distributing the data packets arriving at the corresponding communication line 50 into the correct input queues 12, the input buffer 11 comprises a demultiplexer 19, also called input queue router IQR. For selecting the data packets from the input queues 12 and delivering them via the corresponding input port 20 to the switching device 10 the input buffer 11 comprises a queue selector 21, labelled with QS and serving as a multiplexer. The queue selector 21 selects one of the input queues 12 at any particular point in time and picks one data packet from that input queue 12, and sends it via its input port 20 to the switching device 10. The selecting process is controlled by the input controller 25 which gets its information therefor from the switching device 10. The input controller 25 at a certain point in time signals to the queue selector 21 whether it can send a data packet to the switching device 10 and if yes, from which input queue 12 that data packet can be sent to the switching device 10, respectively to one or more of its output ports 30. The order of fetching the queued data packets from the several input queues 12 is first of all determined by the accessability of the output ports 30, i.e. their occupation state. When an output port 30 is idle, it is ready to receive a data packet and this is signalled to the input controller 25. The input controller 25 works as a queue arbiter by selecting which data packet from which input queue 12 at which time to send from the input buffer 11 to the switching device 10. One such input buffer 11 is arranged per input port 20.
Multicast data packets can be distributed at the demultiplexer 19 by making an entry into each input queue 12 whose corresponding output port 30 is denoted in the data packet destination header. This means that the multicast data packet is copied and entered itself into each such input queue 12. This also means that each multicast data packet heading for a number of n different output ports 30 is copied and queued such that in total n copies thereof reside in the input buffer 11 where the multicast data packet arrived. On the side of the queue selector 21 the principle of fetching only one data packet at a time can be altered in that for multicast data packets it is allowed to send several copies thereof to the switching device 10 at once. This reduces blocking effects to the multicast data packet. With other words, the disadvantage introduced by copying and distributing of a multicast data packet, which takes place at the demultiplexer 19, is countereffected by the advantage of merging several payload-equal packets into one forwarding process at the queue selector 21. Alternatively, such a multicast data packet can be stored only in one of the input queues 12 or in a separate multicast queue and be read out nondestructively from there to all its destination output ports 30.
The switching device 10 comprises for each input port 20 a separate switching section. Each such switching section comprises a set of output buffers 35 and for each of the output buffers 35 a separate input router 13 at their input side and a