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DIFFERENTIAL CHARGE PUMP CIRCUIT WITH HIGH DIFFERENTIAL AND LOW COMMON MODE IMPEDANCE
FIELD OF THE INVENTION The present invention relates to a differential amplifier having high differential impedance and low common mode impedance.
BACKGROUND OF THE INVENTION.
In general, a differential amplifier, or difference amplifier, receives two signals as inputs, and outputs either the current or voltage difference between the input signals. One problem associated with differential ampli- 15 fiers is that they exhibit common mode sensitivities. Common mode sensitivities are defined as the dependency of the output common mode voltage on the change in any parameter in the circuit, such as device mismatch. Some differential amplifiers have common 20 mode sensitivities that are of the same order as the differential gain of the amplifier.
FIG. la illustrates a typical prior art high gain differential amplifier. The output is coupled from the drains of transistors Tl and T2. As is well known in the art, the 25 incremental differential gain of the circuit illustrated in FIG. la is infinitely large if the current source drain loads are perfect, and if transistors Tl and T2 have zero differential output conductance. Although the incremental differential gain is infinite, the differential ampli- 30 fier also exhibits infinite common mode sensitivity. The infinite common mode sensitivity is a result of the mismatch between the sum of the drain load currents, labeled IDL on FIG. la, and the value of the current source at the common source connection. If the drain 35 load currents are not precisely equal, the common mode output voltage approaches the value of either Vdd or
To mitigate the problem of common mode sensitivity, a feedback bias circuit may be employed as shown in 40 FIG. lb. In the circuit of FIG. lb, the common mode output voltage, labeled Va+Vb, is compared with a reference voltage labeled Vre/. Any error detected between the desired and actual common mode output levels generates a correction signal that is fed back to 45 control the current source at the common source connection, driving the output voltage to the correct value. Although use of a feedback loop solves the current source biasing problem, the feedback loop generates new problems. For example, the feedback loop intro- 50 duces complexity to the circuit operation. In addition, a feedback loop inherently exhibits limited bandwidth, thereby placing constraints on the time required to obtain steady state operation when the differential amplifier is powered on and off. The ability to rapidly 55 obtain steady state operation is particularly important in order to extend battery life in portable equipment where it is desirable to activate only those circuits that are in use at a particular moment in time.
Differential amplifiers, when overdriven, also have 60 application for use in charge pump circuits. A charge pump is a circuit, for example, a CMOS circuit, which receives two signals as inputs and generates a voltage across the capacitor indicative of the phase difference between the two input signals. An example of a circuit 65 that uses a charge pump is a phase-locked loop circuit. In such a circuit, a charge pump is used to integrate the phase error between the desired phase and the phase
output. A perfectly lossless charge pump provides a theoretically infinite output if there is non-zero phase error.
A perfectly lossless charge pump enables the attainment of theoretically zero phase error (assuming that there are no other error sources), since any finite output can be obtained with a zero value input.
A lossy charge pump, however, requires a non-zero phase error in order to produce a finite output, and hence, a static phase error results. It is therefore desirable to reduce to an absolute minimum any loss in the charge pump.
An idealized prior art technique is shown in the MOS circuit of FIG. 2a. In this circuit, current sources are utilized as high-impedance loads. Transistors Tl and T2 are assumed to be driven by signals that are sufficiently large in amplitude to switch substantially all of the current 21 of the current source alternately through Ml and M2, so that a net current of I or —I flows through the capacitor. This differential circuit requires some means, however, to set the common-mode level of the output voltage (i.e., the average voltage of the drain terminals of Tl and T2).
One method to provide this is through the use of common-mode feedback bias control loop, as shown in the example of FIG. 2b. In the circuit shown in FIG. 2b, the DC value of the output voltage is compared with a reference voltage, and feedback is arranged to adjust the value of the current source to control the commonmode output voltage. However, stability for the common-mode loop is an issue. Additionally, some reference voltage (either explicit or implicit) is needed to set the value of the common-mode output voltage. Furthermore, the biasing circuit consumes substantially additional die area on a relative basis. Finally, in some applications, it is desirable for the common-mode value of the output to lie within fairly narrow bounds, even when the charge pump is turned off. Use of a commonmode loop is impractical in such a case, since, without power, there is no active loop and the value does not lie within narrow bounds.
SUMMARY AND OBJECTS OF THE
Therefore, it is an object of the present invention to provide a differential amplifier that possesses low common mode sensitivities.
It is another object of the present invention to provide a s differential amplifier that operates down to low supply voltages.
It is another object of the present invention to provide a differential amplifier possessing a rapid transition from a disabled state to an enabled state.
It is another object of the present invention to provide a differential charge pump circuit that operates with low leakage.
It is another object of the present invention to provide a differential charge pump that operates down to low supply voltages.
Furthermore, it is an object of the present invention to provide a charge pump circuit, which provides welldefined bounds on the common-mode value of the output voltage when powered down.
These and other objects of the present invention are realized in an arrangement including a high gain low voltage differential amplifier exhibiting extremely low common mode sensitivities. The differential amplifier
contains a first and second transistor each comprising a first terminal for receiving a supply current, a second terminal for dispensing the supply current, and a third terminal for controlling the amount of supply current flowing from the first terminal to the second terminal. 5 Differential signals are input to the third terminal on the first and second transistors. A power supply, for providing electrical power to the circuit, generates Vdd and Vss voltages. A positive differential load resistance is generated and is connected from the power supply to 10 the first terminal of the first transistor and to the first terminal of the second transistor. To offset the positive differential load resistance, a negative differential load resistance is generated and connects the power supply to the first terminal of the second transistor and to the 15 first terminal of the first transistor. The output signal is generated from the first terminal of the first transistor and from the first terminal of the second transistor. Consequently, the output of the differential amplifier exhibits low common-mode impedance so as to reduce 20 common-mode sensitivities.
For operation as a charge pump circuit, the differential amplifier contains at least one capacitor for generating a capacitance across the first terminal of the first transistor and the first terminal of the second transistor. 25 Control signals are input to the third terminals of the first and second transistors so as to permit switching current, in both directions, from the positive differential load resistance and the negative differential load resistance across the capacitance. 30
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.
BRIEF DESCRIPTION OF THE DRAWINGS 35
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which: 40
FIG. la shows a prior art idealized differential amplifier;
FIG. lb shows a prior art differential amplifier with common-mode feedback bias;
FIG. 2a shows a prior-art differential charge pump; 45
FIG. 2b shows a prior-art differential charge pump with common-mode feedback bias;
FIG. 3 shows a high gain differential amplifier configured in accordance with the present invention;
FIG. 4 shows one embodiment of the differential 50 charge pump of the present invention;
FIG. 5 shows another embodiment of the differential charge pump of the present invention.
A high gain low voltage differential amplifier exhibiting extremely low common mode sensitivities is described. The differential amplifier contains six metal oxide semiconductor field effect transistors (MOSFETs). The high gain and low common mode sensitiv- 60 ity characteristics of the differential amplifier are obtained through a load element. The load element includes a positive differential load resistance and a negative differential load resistance. In one embodiment, the negative and the positive differential load resistances 65 are configured to offset one another. The load element possesses an ideally infinite differential resistance, and low common mode resistance of the order of the recip
rocal transconductance of the MOS devices. Because the load element presents a low common mode impedance, the need for common mode feedback is eliminated.
The differential amplifier has application for use in a differential charge pump circuit. The high differential impedance of the differential amplifier allows the attainment of extremely small leakage, while a low commonmode impedance results in simplified biasing.
FIG. 3 shows a low voltage differential amplifier 300. The low voltage differential amplifier 300 contains six metal oxide semiconductor field effect transistors (MOSFETs). Although embodiments of the invention are described in conjunction with a complementary metal oxide semiconductor (CMOS) configuration, other devices, such as bipolar transistors may be used without deviating from the spirit and scope of the invention. Input signals, labeled Inputi and Input2 on FIG. 3, are input to the gates of transistors Ml and M2, respectively. The differential amplifier 300 is connected to a first power source, having a voltage of Vjj, and a second power source having a voltage of Vss- An output for the differential amplifier 300 is taken from the drains of transistors Ml and M2 labeled Vfland V^on FIG. 3. The differential amplifier 300 illustrated in FIG. 3 is a high gain differential amplifier exhibiting extremely low common mode sensitivities, on the order of unity. The high gain and low common mode sensitivity characteristics of S the differential amplifier 300 are obtained by coupling a high differential resistance, but a low common mode resistance, from the first power source to the drain of transistors Ml and M2.
The load element of the present invention comprises p-channel MOSFET transistors M3, M4, M5 and M6. The load element couples the first power source to the drains of transistors Ml and M2. The load element possesses an ideally infinite differential resistance, and low common mode resistance of the order of the reciprocal transconductance of the MOS devices. The transistors M3 and M6 are diode connected such that the gates are coupled to the drains of the respective devices. Consequently, transistors M3 and M6 together comprise a very low differential resistance.
The gate of transistor M3 is coupled to the gate of transistor M4, and the gate of transistor M5 is coupled to the gate of transistor M6. Because the gates of transistors M3 and M4 are connected, ideally transistor M4 mirrors the current of transistor M3. The drain of transistor M4 is coupled to the drain of transistor M2 so that the mirrored current through M4 flows through M2. By mirroring the current through transistor M3, which is responsible for the low differential resistance, no differential current is generated.
In effect, transistors M4 and M5 serve as a negative differential resistance. Similarly, transistor M5 mirrors the current of transistor M6. The current flowing through transistor M6 is provided at the drain of transistor Ml. Effectively, transistors M3 and M6 constitute a positive differential resistance. Therefore, the high differential resistance is generated because the negative differential resistance, generated by transistors M4 and M5, cancels the positive differential resistance generated by transistors M3 and M6.
Because transistors M3-M6 present a low common mode impedance, the need for common mode feedback is eliminated. The output common mode level of the differential amplifier 300 is one p-channel source to gate voltage drop below the power supply, V</</. If the cur
rent supplied to the differential amplifier 300 is elimi- transistors M3, M4, M5, M6 is ideally infinite, leaving nated, the common mode output voltage cannot drift only finite differential output resistance of the driving far from the value retained when the circuit was active. pair Ml, M2, and the inherent capacitor leakage as Consequently, power up recovery upon reactivation differential loss mechanisms.
occurs quickly because the differential amplifier 300 5 In practice, however, mismatches in the transistors does not utilize common mode feedback bias which cause departures from ideal behavior. Hence, it is desirrequires a feedback loop to settle. In a first embodiment, able to choose the effective resistance of the diode-contransistors M3-M6 are constructed substantially identi- nected devices M3, M6 as high as possible such that any cal in size so that the negative differential load resis- imperfect cancellation by respectively M4, M5, will tance cancels the positive differential. 10 have a proportionally smaller effect. The effect of finite
In another embodiment of the differential amplifier of differential output resistance of Ml, M2, is usually negthe present invention, transistors M3 and M<5 are con- ligible, because there is an inherent cascoding effect by structed substantially identical in size, and transistors Ml, M2 on the current source. The charge pump M4 and M5 are constructed substantially identical in switches all the current 21 into the integrating capacisize. Unlike the first embodiment of the present inven- 15 tance by the control input signals in either a positive or tion, the transistor pair M4 and M5 is mismatched from negative direction. For example, if Ml is turned on and the transistor pair M3 and M6. By mismatching the M2 is turned off, transistor Ml acts as a cascoding detransistors comprising both the negative differential vice for the current source (which source is assumed to resistance and the positive differential resistance, a con- be realized with a transistor or collection of transistors), trolled gain other than infinity is realized. In addition, 20 boosting the effective impedance, this embodiment preserves the attribute of low common This argument applies symmetrically to the case mode sensitivity. For this embodiment of the differen- where M2 is on and Ml is off. Hence, the leakage rial amplifier, the negative differential resistance of tran- caused by Ml, M2 is generally negligible. Further adsistor pair M4 and M5 does not precisely cancel the vantage of the invention is that the common-mode outpositive differential resistance of transistor M3 and M6, 25 put voltage of the charge pump is simply lower than the leaving a finite residual differential resistance. The finite positive supply voltage by one source-to-gate voltage of residual differential resistance may comprise a positive a P-channel device.
or a negative resistance, depending on the relative mag- Therefore, if the charge pump is ever disabled, for nitudes of the individual resistances comprising the load example, by shutting off the current source, recovery is elements. 30 relatively quick because common-mode levels cannot
The embodiments of the present invention have use in be moved far from their equilibrium active values, a variety of applications. For example, the differential FIG. 5 shows a second embodiment of the charge amplifier has application for use in a differential charge pump circuit of the present invention. For this embodipump circuit. One embodiment of a low leakage CMOS ment, an alternate connection of the integrating capacicharge pump circuit of the present invention, is illus- 35 tance is employed. For some circuits, the most area-effitrated in FIG. 4. For other embodiments, other types of cient capacitance is formed from the gate structure of a devices may be used. MOS transistor. Such capacitors require DC bias that is
In the embodiment shown in FIG. 4, the load is in excess of approximately one threshold voltage to formed of a quad of P-channel MOS devices. As ex- maximize capacitance and to avoid excessive nonlinearplained above in conjunction with the differential am- 40 ities. In this embodiment, the biasing criteria is satisfied plifier 300, transistors M3 and M6 are diode-connected, by splitting the capacitor into two equal capacitors and and are located in parallel with cross-connected transis- coupling each capacitor to V^. By connecting each tors M4 and M5. For use in a charge pump circuit, capacitor to Vss, this embodiment provides filtering of transistors M3, M4, M5 and M6 are all made to be sub- power supply (Vdd) noise. Any noise on the positive stantially of the same size. An integration capacitance 45 power supply that couples through the p-channel load Ci is shown as a single device connected to the drains of devices is bypassed by the capacitors, reducing greatly the drive transistors Ml and M2. the amount of the noise passed on to any subsequent
The signals driving the gates of drive transistors Ml stage, and M2 are assumed to be large enough in amplitude to Thus, a differential charge pump that employs a load switch substantially all of the current 21 of the current 50 device that possesses high differential impedance, but a source into the integrating capacitance Ci. very low common-mode impedance, is described. The
The diode-connected devices, M3, M6, together pres- high differential impedance allows the attainment of ent a positive differential resistance. The positive differ- extremely small leakage, while low common-mode imential resistance by itself provides an undesirable leak- pedance results in simplified biasing, age path for the integrating capacitance. To mitigate 55 In the foregoing specification, the invention has been this leakage, the current through M3, M6 is canceled by described with reference to specific exemplary embodithe function of transistors M4, M5, which function can ments thereof. It will, however, be evident that various be viewed as that of a negative resistance. Thus, transis- modifications and changes may be made thereto withtors M4, M5 cancel out the leakage of M3, M6 in the out departing from the broader spirit and scope of the following manner. 60 invention as set forth in the appended claims. The speci
Transistors M3 and M4 comprise a current mirror. fication and drawings are, accordingly, to be regarded Assuming ideal behavior, the two devices carry the in an illustrative rather than a restrictive sense, same current. Because the drains of devices M3 and M4 What is claimed is:
are connected to opposite sides of the capacitance, the 1. A differential charge pump circuit comprising: net contribution by this connection to the differential 65 first and second transistors each comprising a first current is zero. By symmetry, the same reasoning ap- terminal for receiving a supply current, a second
plies to the current mirror formed by transistors M5, terminal for dispensing said supply current, and a
M6, so that the net differential resistance presented by third terminal for controlling the amount of supply