result, debugging operations using an ICE in a system STRUCTURE AND METHOD FOR MONITORING with an on-chip cache memory can be very difficult.
AN INTERNAL CACHE When the on-chip cache memory achieves a high hit
ratio, only the relatively infrequent accesses to main FIELD OF THE INVENTION 5 memory due to cache misses or references to uncachea
This invention relates to integrated circuits, and in ble portions of memory can be monitored from the pins, particular, relates to the design of microprocessors. In the prior art, to provide a way for the ICE to
monitor execution of the instruction stream, or to introDESCRIPTION OF RELATED ART duce alternative instructions into the CPU, designers of
Exploiting the property of locality of memory refer- 10 microprocessors with on-chip cache memory often ences, cache memories have been successful in achiev- provide means for disabling the on-chip cache, so that ing high performance in many computer systems In the every instruction can be monitored from the off-chip past, cache memories of microprocessor-based systems bus between the main memory and the microprocessor, are provided off-chip using high performance memory Debugging under a disabled cache, however, is a condicomponents. This is primarily because the amount of 15 tion which does not reflect the intended operation of silicon area necessary to provide an on-chip cache the microprocessor. Consequently, considerable overmemory of reasonable performance would have been head, which is especially undesirable for testing real impractical, since increasing the size of an integrated time applications, is introduced into program execution, circuit to accommodate a cache memory will adversely For such applications, it is often necessary to use, for impact the yield of the integrated circuit in a given 20 exampie> a technique called a "shadow cache," i.e. an manufacturing process. However, with the density externally implemented cache memory which mirrors achieved recently in integrated circuit technology, it is identically the operation of the on-chip cache. A technow possible to provide on-chip cache memory eco- njque such as shadow cache requires both expensive nomically. hardware and complex software.
In a computer system with a cache memory, when a 25 memory word is needed, the central processing unit SUMMARY OF THE INVENTION
(CPU) looks into the cache memory for a copy of the A structure and a method are provided to bring the memory word. If the memory word is found m the jnternal sJ ,s of an int ated circuit t0 the external cache memory, a cache hit is said to have occurred, ms for monitori p . In
one embodiment, the
and the main memory is not accessed. Thus, a FIGURE 30 , °iL k...,,m„ „„ „i.- „„i.» j
, .... . rr signals on an internal bus between an on-chip cache and
of merit which can be used to measure the effectiveness „ r-m: ;„ „ ,„„„„„„ „ •. , r\. ■
, . T-i. • a CPU m a microprocessor are provided on the micro
of the cache memory is the hit ratio. The hit ratio is , ;.... , ^ , ,,
the percentage of total memory references in which the Pr°ceSfS°r * P.ins ;°r * Kdata/address *>us' desired datum is found in the cache memory without ?he" *f bidirectional data/address bus is not used for accessing the main memory. When the desired datum is 35 data/address bus transactions with the main memory or not found in the cache memory, a "cache miss" is said to the peripheral mput/output devices. When the bidirechave occurred and the main memory is then accessed fI0nal data/address bus is providing the signals on the for the desired datum. In addition, in many computer mternal bus'tne 0UtPut contro1 s,Snals which the microsystems, there are portions of the address space which processor provides to the main memory or the penphare not mapped to the cache memory. These portions of 40 efal mput/output devices are disabled. In this embodithe address space are said to be "uncached" or "unc- ment> reserved pins are used to selectively enable the acheable". For example, the addresses assigned to in- address/data bus to bring to the external pins the signals put/output (I/O) devices are almost always uncached. on tne internal bus.
Both a cache miss or an uncacheable memory reference Tne present invention allows testing equipment to result in an access to the main memory. 45 monitor internal signals of an integrated circuit, such as In the course of developing or debugging a computer the signals on an internal bus between an on-chip cache system, it is often necessary to monitor program execu- memory and a CPU in a microprocessor, using the tion by the CPU or to interrupt one instruction stream external pins of the integrated circuit. The present into direct the CPU to execute certain alternate instruc- vention supports standard testing equipment such as a tions. For example, a technique for testing a micro- 50 logic analyzer or an in-circuit emulator, without the use processor in a system under development uses an in-cir- of techniques such as "shadow caches", and thereby cuit emulator (ICE) which monitors the instruction obviates the need of expensive hardware, or complex stream and, where appropriate, takes control of the software techniques for monitoring such internal sigmicroprocessor by forcing the microprocessor to exe- nals. In addition, because internal caches need not be cute an alternative program. To achieve this end, the 55 disabled, the present invention allows testing of the ICE monitors the signals on the microprocessor's pins. integrated circuit under conditions closer to real time When a monitored instruction in the program execution applications than previously attained by the prior art. is encountered, the ICE causes alternative instructions The present invention is better understood upon considto be executed for such purpose as reading or altering eration of the below detailed description and the acthe internal state of the CPU. Hence, when the cache 60 companying drawings.
memory is implemented off-chip, the transactions be- Dnirr Tm=o/~t> 1111-1/TM <-.r? -mr .,,,,^0 tween the cache memory and the CPU can be moni- BRIEF DESCRIPTION OF THE DRAWINGS tored by the ICE via the microprocessor's pins on the FIG. la shows a computer system 100 having a prooff-chip bus between the cache memory and the CPU. cessor 101 with an on-chip instruction cache system 102 However, when the cache memory is implemented 65 and a main memory system 150 external to the proceson-chip, the transactions between the cache and the sor 101, in accordance with the present invention. CPU occur on an internal on-chip bus, which cannot be FIG. lb is a block diagram of the processor 101 of probed from .the pins of the integrated circuit. As a FIG. la.