GRAPHICS CONTROLLER INTEGRATED
CIRCUIT WITHOUT MEMORY INTERFACE
PINS AND ASSOCIATED POWER
This is a continuation of application Ser. No. 08/581,086, filed Dec. 29, 1995, now abandoned, which was a Rule 60 Divisional of Ser. No. 08/262,412, filed Jun. 20, 1994, also abandoned.
BACKGROUND OF THE INVENTION
This invention is related to graphics controller systems and, more particularly, to graphics controller systems with low power dissipation.
As shown in FIG. 1, a typical graphics controller system has a graphics controller integrated circuit 10, which has a graphics engine 12 for manipulating video data, and a CPU interface 13, display interface 14 and video memory interface 15. The graphics controller integrated circuit 10 receives video image data from a CPU (central processing unit) through the CPU interface 13, and after processing the data, stores that information through the video memory interface 15 in a separate video memory 11, also called the video frame buffer. The graphics controller 10 also makes sure that the image data is regularly retrieved from the video memory (through the interface 15) and fed to a display unit through the display interface 14 with a frequency which satisfies the refresh requirements of the display. In some more advanced graphics controller systems, video image data may also be received from other sources, such as a device with a PCMCIA (Personal Computer Memory Card International Association) connector.
The video memory interface 15 of the graphics controller integrated circuit 10 has ports dedicated to interface with the video memory 11. The number of ports required for this interface 15 is the sum of the address, data and control signals required to access the video memory 11. The memory 11 has a size which is a function of the video frame buffer required to support the display resolution. While dynamic random access memory (DRAM) is most commonly used for the video frame buffer, some high performance systems use VRAMs (DRAMs with serial data ports added). A typical VGA (Video Graphics Adapter standard) display in an IBM-compatible mobile computer, often called a notebook computer, with an LCD (liquid crystal display) panel uses a single 256 Kxl6 DRAM integrated circuit as a video frame buffer. A typical SVGA (Super VGA standard) system uses two such DRAMs organized as 256 Kx32.
Wider data paths between the video memory and the graphics controller allow greater bandwidth for data transfer. However, the wider data paths also increase the pin count of the graphics controller package and the package count of the DRAMs with the accompanying increased manufacturing complexity and costs. A 16-bit data path requires one DRAM package and approximately 30 signal lines to handle the memory address, data, and control signals, while a 32-bit data path requires two DRAM packages and 50 signal lines. Power dissipation is increased as more signal lines are added since each signal line has a parasitic capacitance associated with the package I/O pin, as well as with the conducting trace on the motherboard of the mobile computer system. Therefore, an increase in graphics performance is accompanied by an increase in power dissipation, pin count and package count.
The present invention solves or substantially mitigates these problems with a high performance graphics controller
system having low power dissipation, and low pin and package counts.
SUMMARY OF THE INVENTION
According to the invention, there is provided a graphics controller system with increased performance simultaneously with a reduction in power dissipation, point count and package count. Previously external video memory is integrated with the graphics controller system to eliminate the memory interface. The reduction in pin count is used to add the pins associated with a PCMCIA host adapter and thus allow the integration of that function on the same chip, so as to further reduce the package count on the mother board.
The present invention also provides for particular arrangements for logic circuits and output buffer circuits so that large amounts of logic circuitry sufficient to perform graphics controller system functions may be integrated with the large amounts of memory sufficient to act as a high performance video memory. Furthermore, the present invention provides for a wide bus between the integrated video memory and the functional blocks of the graphics controller system. The present invention has circuits in these blocks for manipulating the video data from the wide bus so that data transfer remains compatible to the various operational VGA modes.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates the general organization of a graphics controller system in the prior art;
FIG. 2 illustrates the general organization of a graphics controller integrated circuit according to the present invention;
FIG. 3A is a circuit diagram of a CMOS logic inverter as connected in a prior art integrated circuit manufactured according to a logic process; FIG. 3B is a circuit diagram of a CMOS logic inverter as connected in a prior art integrated circuit manufactured according to a DRAM process;
FIG. 4 is a circuit diagram of a CMOS logic inverter as connected according to the present invention in an integrated circuit manufactured according to a DRAM process;
FIG. 5 is a cross-sectional diagram of a P-channel transistor in an N-type well, which form most of the analog circuits in the graphics controller portion of the integrated circuit shown in FIG. 2;
FIG. 6A is a circuit diagram of a CMOS driver stage of an output buffer found in the prior art; FIG. 6B is a circuit diagram of a CMOS driver stage of an output buffer according to the present invention;
FIG. 7 is a block diagram detailing the organization of a graphics controller system according to the present invention;
FIG. 8 illustrates the organization of the output signals of the Bus Read Latch of the graphics controller system of FIG. 7; and
FIGS. 9A-9D illustrate the organization of the multiplexer at the output of the Bus Read Latch of the graphics controller system of FIG. 7.
DESCRIPTION OF THE PREFERRED
In accordance with the present invention, the graphics controller functions are integrated on the same integrated circuit substrate as the video memory, as shown in FIG. 2.