METHOD AND APPARATUS FOR
CLOCK-AND-DATA RECOVERY USING A
SECONDARY DELAY-LOCKED LOOP
BACKGROUND OF THE INVENTION 5
1. Field of the Invention
The present invention generally relates to clock-and-data recovery systems where a periodic clock signal is to be extracted from non-periodic data, and the same clock is then 10 used to sample data with a minimum of errors.
2. Description of the Related Art
Phase-locked loop circuits play a critical role in high speed data communications. They are used in clock-anddata recovery circuits, in which clock and data are recovered 15 from a single high-speed serial stream of non-return-to-zero data. Ethernet, Fibre Channel, and SONET/SDH transmission systems are specific examples of systems that typically use phase-locked loop-based clock-and-data recovery circuits. 20
FIG. 1 shows a block diagram of a conventional phaselocked loop-based clock-and-data recovery 10, which has a phase detector 12, a loop filter 14, and a voltage-controlled oscillator 16. The phase-locked loop-based clock-and-data recovers circuit 10 is connected to a D-type flip-flop 18. The 25 phase detector 12 receives the clock data stream and the clock signal from the voltage-controlled oscillator 16, and compares the timing difference between the data transition in the data stream and the clock edge from the voltagecontrolled oscillator 16. The phase detector 12 then gener- 30 ates an error voltage to tune the voltage-controlled oscillator frequency.
Conventional phase detectors 12 are usually also accompanied by a charge pump (not shown) in modern integrated circuit design. The loop filter 14 between the phase detector 35 12 and the voltage-controlled oscillator 16 rejects high frequency noise that is embedded in the incoming data.
The feedback operation shown in FIG. 1 forces the clock edge from the voltage-controlled oscillator to be aligned to the data transition in steady state, and the D-type flip-flop 18 40 samples the data with the recovered clock signal. To reduce the bit-error rate of the communications link, the data should be retimed in such a way that the clock edge that is used to sample data is aligned to the middle of the data bit period.
In clock-and-data recovery systems, noise is an overriding 45 design concern. For a phase-locked loop, noise is quantified by measuring the jitter of the phase-locked loop output. For example, for SONET applications, the jitter transfer function is important and is required to have less than a 0.1 dB peaking at 3 dB corner frequency. Jitter peaking should be 50 avoided when a phase-locked loop is used repeatedly, as in a SONET application, since it amplifies jitter at a certain frequency band where peaking occurs in jitter transfer function. The peaking at the 3 dB corner frequency usually happens if the loop dynamic of the phase-locked loop is not 55 well designed, which is one of the reasons that prevent phase-locked loop bandwidth from being widened. Thus, to design a low-jitter phase-locked loop is challenging in many ways due to stringent jitter budgets and loop bandwidth specifications. The phase-locked loop in a clock-and-data 60 recovery circuit provides three functions: (a) it filters out noise in the data channel: (b) it extracts clock information: and (c) it tracks the jitter of the data for better data retiming. Having the data sampled by a single D-type flip-flop, conventional phase-locked-loop based clock-and-data 65 recovery circuits provide instant data retiming with the recovered clock signal.
To accommodate high-frequency timing variation of the data edge, the phase-locked loop needs to exhibit an agile response to track the short-term jitter using wide loop bandwidth. However, wide loop bandwidth can limit the noise-filtering from the data channel as the noise bandwidth increases. As the clock is perturbed by unwanted channel noise, the bit-error rate will increase simply due to the clock itself Therefore, there is a fundamental tradeoff in choosing loop bandwidth between the clock extraction and the data retiming.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, drawbacks, and disadvantages of the conventional methods and structures, an object of the present invention is to provide a method and structure in which a clock and data recovery circuit includes a delay-locked-loop adapted to recover data from a data stream and a phase-locked-loop in communication with the delay-locked-loop and adapted to recover a clock signal from the data stream.
An object of the present invention is to prevent perturbing the clock by unwanted channel noise.
In a first aspect of the present invention, a clock and data recovery circuit includes a delay-locked-loop adapted to recover data from a data stream: and a phase-locked-loop in communication with the delay-locked-loop and adapted to recover a clock signal from the data stream.
In a second aspect of the present invention, a method of recovering clock and data signals from a data stream, includes recovering data from said data stream in a delaylocked-loop: receiving said data stream in a phase-lockedloop from said delay-locked loop: and recovering a clock signal from said data stream in said phase-locked-loop.
In a third aspect of the present invention, a circuit for recovering clock and data signals from a data stream, includes means for extracting a clock signal from the data stream: and means for extracting data from a data stream, wherein the means for extracting said clock signal and the means for extracting data are independent to optimally allocate bandwidth.
In a fourth aspect of the present invention, a circuit for recovering clock and data signals from a data stream, includes means for recovering data from the data stream in a delay-locked-loop: means for receiving the data stream in a phase-locked-loop from the delay-locked loop: and means for recovering a clock signal from the data stream in the phase-locked-loop.
With the unique and unobvious aspects of the present invention, a two-part topology performs clock-and-data recovery operations in two steps. The topology employs a delay-locked loop to make the data retiming process independent of a clock signal recovery function, in which the clock signal is extracted from the data channel by a phaselocked loop. The phase-locked loop extracts the clock information from a noisy serial stream of non-return-to-zero data and tracks the long-term jitter, while a delay-locked loop having a wide loop bandwidth performs data synchronization in the phase domain and tracks the short-term jitter. The separation of these functions allows the designer to optimally allocate the loop bandwidth for each function.
With the present invention, one can provide a narrow or moderate bandwidth for the phase-locked loop for a clean clock signal and can provide a wide bandwidth for the delay-locked loop for prompt jitter tracking without creating jitter peaking. With the present invention, the jitter peaking can be avoided with wide loop bandwidth since the delay
