SEMICONDUCTOR DEVICE INCLUDING
BUILT-IN REDUNDANCY ANALYSIS
CIRCUIT FOR SIMULTANEOUSLY TESTING
AND ANALYZING FAILURE OF A
PLURALITY OF MEMORIES AND METHOD
FOR ANALYZING THE FAILURE OF THE
PLURALITY OF MEMORIES
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a built-in redundancy analysis (BIRA) circuit for testing and analyzing the failure of a plurality of memories, that is, a built-in redundancy analysis unit and a method for analyzing the failure of the plurality of memories using the built-in redundancy analysis unit.
2. Description of the Related Art
Contemporary integrated circuits, or chips are commonly designed and manufactured using deep sub-micron (DSM) technology. As an increasing amount of memory becomes built-in, or integrated, into the chip circuitry, the yield of the memory component significantly affects the yield of the entire chip. Accordingly, a repairable memory is necessary in order to improve yield.
Also, as semiconductor devices become more highly integrated and their functions become more complicated, various new methods must be developed for effectively testing them. In particular, a built-in self test (BIST) method has been developed in order to effectively test a memory that is built into a semiconductor memory device. In this method, a built-in memory is tested using a circuit in which a memory test algorithm is realized.
A built-in redundancy analysis (BIRA) technology which, unlike the BIST for testing memories, is capable of extracting information on testing, analyzing the failure of, and repairing built-in repairable memories using a BIST test method, has recently appeared. Namely, after testing memories using the BIST and storing information on failure, the memories are repaired through the built-in self repair (BISR) method and the repairing result is output using a scan chain. A method of dividing a block of memory into many smaller blocks and simultaneously testing the blocks and analyzing the failure of the blocks is used. This method has an advantage in that the time spent on testing the blocks and analyzing the failure of the blocks can be reduced when the size of a memory is large.
When a memory is tested and analyzed using the abovementioned conventional methods, various memories having different sizes must be separately tested and analyzed. Also, in the method of storing a failure generated in the respective test circumstances and comparing the failures with each other, a process of separately analyzing the failures additionally generated according to circumstances is necessary since the failure found in the worst circumstance and the failure found in the best circumstance cannot be analyzed at one time when they are different from each other. The method of dividing a memory block into many smaller blocks and simultaneously testing the blocks and analyzing the failure of the blocks has a disadvantage in that the area required for simultaneously processing the divided blocks becomes large when many memories are tested. Namely, according to the above-mentioned conventional methods, it is possible to effectively test and analyze a single memory, however, the conventional methods are disadvantageous in
testing and analyzing chips that include multiple memory blocks having different sizes, because of limitations in the test time and the number of pins.
5 SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a semiconductor device including a built-in redundancy analysis (BIRA) circuit, that is, a BIRA unit which is capable of reducing the time taken to test a memory and the number 10 of pins of the memory by simultaneously testing and analyzing the failure of a plurality of memories.
It is a second object of the present invention to provide a method for analyzing the failure of the plurality of memories, which is capable of reducing the test time and the number of pins by simultaneously testing and analyzing the failure of a semiconductor device including a plurality of memories.
Accordingly, to achieve the first object, there is provided 20 a semiconductor device comprising a plurality of memory blocks, a plurality of built-in redundancy analysis units, and a controller.
The plurality of built-in redundancy analysis units outputs a group of failure repairing information signals by testing
25 and analyzing a corresponding memory block among the plurality of memory blocks in response to common driving signals and each of a plurality of separate, independent, selection signals.
The controller generates the common driving signals and
30 the respective separate selection signals in response to a plurality of externally applied control signals and sequentially receives and sequentially outputs the group of failure repairing information signals generated by the respective built-in redundancy analysis units.
35 Each of the built-in redundancy analysis units comprises a control signal generator, a data generator, a comparator, and a failure analysis unit.
The control signal generator generates a control signal for controlling the testing and analyzing operations and some of
40 a group of failure repairing information signals in response to some of the common driving signals and some of the separate selection signals.
The data generator is controlled by the control signal
45 generator and generates data input signals for testing a corresponding memory block among the memory blocks and comparison data to be compared with read data read from the memory.
The comparator is controlled by the control signal gen
50 erator and compares read data read from the memory block with the comparison data.
The failure analysis unit is controlled by the control signal generator and receives a data failure signal generated by the comparator in response to other signals among the separate
55 selection signals and other signals among the common driving signals and generating other signals among a group of failure repairing information signals.
To achieve the second object of the present invention, there is provided a failure analyzing method with respect to
60 a semiconductor device comprising a plurality of memory blocks, comprising the steps of: (a) applying a plurality of externally paplied control signals; (b) generating common driving signals and each of the separate selection signals in response to the control signals; (c) testing and analyzing the
65 respective memory blocks and generating and storing a group of failure repairing information signals with respect to the memory blocks in response to the common driving
signals and each separate selection signal; and (d) sequentially receiving the group of failure repairing information signals and sequentially outputting the group of failure repairing information signals to the outside of the semiconductor device. The failure analyzing method may further 5 comprise the step of: (e) simultaneously performing a retention test on the plurality of memory blocks in response to the common driving signals.