I/O ADAPTER LPAR ISOLATION WITH
ASSIGNED MEMORY SPACE
CROSS REFERENCE TO RELATED
U.S. patent application Ser. No. 11/621,279, entitled "I/O Adapter LPAR Isolation in a Hypertransport Environment Employing a Content Addressable Memory", and Ser. No. 11/621,314, entitled "I/O Adapter LPAR Isolation in a Hyper- l o transport Environment with Assigned Memory Space Indexed via a TVT and Unit IDs", filed concurrently herewith are assigned to the same assignee hereof, International Business Machines Corporation of Armonk, N.Y., and contain subject matter related, in certain respect, to the subject matter 15 of the present application. U.S. patent application Ser. No. 11/550,618, entitled "I/O Adapter LPAR Isolation in a Hypertransport Environment" filed Oct. 18, 2006, and assigned to the same assignee hereof, also contains subject matter related, in certain respect, to the subject matter of the present appli- 20 cation. The above-identified patent applications are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to isolating input/output adapter addressing domains in a data processing system. More specifically, the invention relates to isolating input/ output adapter addressing domains in a logically partitioned 30 data processing system implementing HyperTransport. The term "isolation", as used herein, refers to verifying that an I/O adapter actually owns or has the right to access particular system memory locations for which it is requesting access. Thus, if an I/O adapter is properly isolated to a preassigned 35 memory space, it will only request access to that area of memory.
2. Background Art
In a logically partitioned data processing system, multiple 40 operating systems or multiple copies of a single operating system are run on a single data processing system platform. Each operating system or operating system copy executing within the data processing system is assigned to a different logical partition ("LPAR"), and each partition is allocated a 45 non-overlapping subset of the resources of the platform. Thus, each operating system or operating system copy directly controls a distinct set of allocatable resources within the platform.
Among the platform resources that may be allocated to 50 different partitions areprocessors ortime slices of processors, regions of system memory, and I/O Adapters ("IOAs") or parts of IOAs. Thus, different regions of system memory and different IOAs or parts of IOAs may be assigned to different partitions, i.e. each IOA is "owned" by a partition. In such an 55 environment, it is important that the platform provide a mechanism to enable IOAs or parts of IOAs to obtain access to all the physical memory that they require to properly service the partition or partitions to which they have been assigned; while, at the same time prevent IOAs or parts of go IOAs from obtaining access to physical memory that has not been allocated to their associated partitions.
In a logically partitioned data processing system, various communication technologies may be used to link together the electronic devices of the system via both physical media and 65 wirelessly. Some communication technologies interface a pair of devices, other communication technologies interface
small groups of devices, and still other communication technologies interface large groups of devices.
One relatively new communication technology for coupling relatively small groups of devices is the HyperTransport (HT) technology. The HT Standard sets forth definitions for a high-speed, low-latency protocol that can interface with today's buses such as AGP, Peripheral component interconnect ("PCI"), 1394, USB 2.0, and 1 Gbit Ethernet as well as next generation buses including AGP 8x, Infiniband, PCI-X, PCI 3.0, PCIe, and 10 Gbit Ethernet. HT interconnects provide high-speed data links between coupled devices. Most HT enabled devices include at least a pair of HT ports so that HT enabled devices may be daisy-chained. In an HT chain or fabric, each coupled device may communicate with each other coupled device using appropriate addressing and control. Examples of devices that may be HT chained include packet data routers, server computers, data storage devices, and other computer peripheral devices.
HT thus offers many important advantages. Using HyperTransport attached I/O bridges in a logically partitioned data processing system, however, requires a way of isolating IOA direct memory access ("DMA") and interrupt requests to the owning LPAR.
Importantly, one LPAR could affect another through an IOA. With logical partitions, an OS in one partition cannot communicate with an OS in another partition through an IOA. For example, one OS may send commands and addresses to an IOA, and the IOA would perform DMA using these addresses. There is no mechanism to check the addresses that are provided by the OS to the IOA. Instead, the BAR/limit (and later, the translation validation table (TVT)) verifies the address when it is presented to the host by the IOA.
SUMMARY OF THE INVENTION
An object of this invention is to provide a method of and system for IOA and LPAR isolation and IOA identification.
A further object of the invention is to assign Unit IDs (HyperTransport defined) to I/O adapters, and to use the assigned Unit IDs to identify each IOA to its owning LPAR.
A further object of the invention is to assign multiple UnitIDs to a PCIe bridge to allow multiple IOAs under the bridge or to allow multiple functions within an IOA to be individually assigned to different LPARs.
These and other objectives are obtained with a data processing system and a method of isolating a plurality of IOAs of that system. The data processing system comprises, in addition to the plurality of IOAs, a set of processors including system memory with a translation validation table ("TVT") and with a content addressable memory ("CAM"). Each of the IOAs is connected to the host bridge and has a respective identifier.
In a preferred embodiment, these identifiers are PCIe defined Requestor IDs and an innovative translation validation table (TVT) implementation for allowing each I/O Adapter to have its own memory space is described herein. The commands issued by the IOAs include a Req ID field for identifying one or more IOAs. The Req ID is used as an input to the CAM which provides an index into the TVT. The TVT specifies the unique and independent system memory space for the IOA.
These, and other, aspects and objects of the present invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the present invention and numerous specific