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A substantially zero overhead mutual-exclusion apparatus and method (90, 120) is provided that allows concurrent reading and updating data while maintaining data coherency. That is, a data reading process executes the same sequence of instructions that would be executed if the data were never updated. Rather than depending exclusively on overhead-imposing locks, this mutual-exclusion mechanism tracks an execution history (138) of a thread (16, 112) to determine safe times for processing a current generation (108, 130, 131) of data updates while a next generation (110, 132, 133) of data updates is concurrently being saved. A thread is any locus of control, such as a processor. A summary of thread activity (106, 122) tracks which threads have passed through a quiescent state after the current generation of updates was started. When the last thread related to the current generation passes through a quiescent state, the summary of thread activity signals a callback processor (104, 124)...

Inventors: John D. Slingwine, Paul E. McKenney
Original Assignee: Sequent Computer Systems, Inc.
Primary Examiner: Matthew M. Kim
Current U.S. Classification: 717/147; 707/799; 707/803; 707/956; 707/999.008; 711/147; 711/158; 718/106
International Classification: G06F 1300

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Claims

1. A mutual-exclusion apparatus for maintaining data coherency while concurrently reading and updating a current generation data element stored in first sites of a memory of a computer, the mutual-exclusion apparatus comprising:

a first thread controlling the reading of the current generation data element;
a second thread controlling the updating of the current generation data element and storing the updated data element in second sites as a next generation data element;
a thread activity monitor producing and storing in the memory, execution history data indicative of states of the first and second threads; and
an element processor processing the current and next generation data elements in response to the execution history data that indicate the first and second threads have one of entered a predetermined state and passed through the predetermined state.

2. The mutual-exclusion apparatus of claim 1 in which the thread activity monitor includes at least one of a bitmask, a dense bitmap, a distributed bitmap, a hierarchical bitmap, and a per-thread quiescent state counter.

3. The mutual-exclusion apparatus of claim 2 in which the thread activity monitor further includes a generation counter.

4. The mutual-exclusion apparatus of claim 2 in which the thread activity monitor further includes a thread counter.

5. The apparatus of claim 1 in which the predetermined state is a quiescent state.

6. The mutual-exclusion apparatus of claim 5 in which the quiescent state includes at least one of an idle loop, a user mode, a context switching point, a wait for user input, a wait for messages, a wait for transactions, a wait for control input, a base priority level, an event queue processor, and an artificially created quiescent state.

7. The mutual-exclusion apparatus of claim 1 in which the element processor processes the first and next generation data elements such that the current generation data element is replaced by the next generation data element.

8. The mutual-exclusion apparatus of claim 1 in which the current generation data elements are tracked by a first callback that is an element of a current generation data structure and the next generation data elements are tracked by a second callback that is an element of a next generation data structure, and the element processor is a callback processor that processes the current generation data elements in accordance with a processing function stored in the first callback and processes the next generation data elements in accordance with a processing function stored in the second callback.

9. The mutual-exclusion apparatus of claim 1 in which each of the first and second threads includes at least one of a processor, a process, a task, an interrupt handler, a service procedure, a co-routine, and a transaction.

10. The mutual-exclusion apparatus of claim 1 in which the element processor processes the current and next generation data elements when at least one of a controlling thread enters a quiescent state, leaves a quiescent state, a reader thread accesses a data structure, an updater thread updates a data structure, and an interrupt is received by the element processor.

11. The apparatus of claim 1 in which the computer is of a multiprocessor type.

12. In a computer system, a method for providing mutual-exclusion between current and next generation data elements, the next generation data element being formed by updating while concurrently reading the current generation data element stored in first memory sites of a computer, the mutual-exclusion method comprising the steps of:

reading under control of a first thread the current generation data element;
updating under control of a second thread the current generation data element to form and store in second memory sites the next generation data element;
monitoring the first and second threads to produce execution history data indicative of states of the first and second threads; and
processing the current and next generation data elements in response to execution history data that indicate the first and second threads have one of entered a predetermined state and passed through the predetermined state.

13. The method of claim 12 in which the execution history data are stored in at least one of a bitmask, a dense bitmap, a distributed bitmap, a hierarchical bitmap, and a per-thread quiescent state counter.

14. The method of claim 13 in which the execution history data are further stored in a generation counter.

15. The method of claim 13 in which the execution history data are further stored in a thread counter.

16. The method of claim 12 in which the predetermined state is a quiescent state.

17. The method of claim 16 in which the quiescent state includes at least one of an idle loop, a user mode, a context switching point, a wait for user input, a wait for messages, a wait for transactions, a wait for control input, a base priority level, an event queue processor, and an artificially created quiescent state.

18. The method of claim 12 further including a step of resetting the execution history data in response to performing the processing step.

19. The method of claim 12 in which the current generation data elements are tracked by a first callback that is an element of a current generation data structure and the next generation data elements are tracked by a second callback that is an element of a next generation data structure, and the processing step further includes processing the current generation data elements in accordance with a processing function stored in the first callback and processing the next generation data elements in accordance with a processing function stored in the second callback.

20. The method of claim 12 in which the processing step comprises replacing the current generation data element with the next generation data element in response to the execution history data indicating that the first and second threads have one of entered a predetermined state and passed through the predetermined state.

21. The method of claim 12 in which each of the first and second threads includes at least one of a processor, a process, a task, an interrupt handler, a service procedure, and a transaction.

22. The method of claim 12 in which the computer system includes at least one of a reader thread, an updater thread, and a callback processor and in which the processing step commences when one of the first and second threads one of enters a quiescent state, leaves the quiescent state, the reader thread accesses a data structure, the updater thread updates a data structure, and the callback processor receives an interrupt.

23. The method of claim 12 in which the computer is of a multiprocessor type.

24. A computer system operating in accordance with the method of claim 12.

Drawings