Testable high count counter

1. An integrated circuit comprising a shift register having n bit locations and having a data input for receiving a data signal, a set input for receiving a set signal, and a clock input for receiving a clock signal;

and further comprising feedback circuitry for feeding back a data signal to said data input when a given pattern of bits is located in said shift register;

characterized in that said integrated circuit further comprises first combinatorial logic circuitry having n inputs connected to said n bit locations, and having an output to indicate that a desired test pattern has been achieved when each bit of the shift register has made all possible state transitions in a number of clock cycles less than 2.sup.n -1;

and further characterized in that said integrated circuit further comprises second combinatorial logic circuitry having n inputs connected to said n bit locations, and having an output to indicate when a count of 2.sup.n -1 clock cycles has been achieved.

2. The invention of claim 1 wherein said feedback circuitry comprises an exclusive OR gate having a first input coupled to a first bit location and a second input coupled to a second bit location, and having an output coupled to said data input.

3. The invention of claim 2 wherein n=20 arranged from bit 19 nearest the data input to bit 0 farthest from the data input, and wherein bit 0 is said first bit location that is coupled to said first input of said exclusive OR gate, and bit 3 is said second bit location that is coupled to said second input of said exclusive OR gate.

4. The invention of claim 1 further comprising a flip-flop having a data input coupled to the output of said first combinatorial circuitry, having a clock input coupled to receive said clock signal, and an output coupled to said set input of said shift register.

5. A computer system having a watchdog timer for indicating the occurrence of a software runaway situation, said watchdog timer including a counter comprising:

a shift register having n bit locations and having a data input for receiving a data signal, a set input for receiving a set signal, and a clock input for receiving a clock signal;

and further comprising feedback circuitry for feeding back a data signal to said data input when a given pattern of bits is located in said shift register;

characterized in that said watchdog timer further comprises first combinatorial logic circuitry having n inputs connected to said n bit locations, and having a test output to indicate that a desired test pattern has been achieved when each bit of the shift register has made all possible state transitions in a number of clock cycles less than 2.sup.n -1;

and further characterized in that said watchdog timer further comprises second combinatorial logic circuitry having n inputs connected to said n bit locations, and having a reset output to indicate when a count of 2.sup.n -1 clock cycles has been achieved, with said reset output being coupled to reset circuitry.

6. The invention of claim 5 wherein said feedback circuitry comprises an exclusive OR gate having a first input coupled to a first bit location and a second input coupled to a second bit location, and having an output coupled to said data input.

7. The invention claim 6 wherein n=20 arranged from bit 19 nearest the data input to bit 0 farthest from the data input, and wherein bit 0 is said first bit location that is coupled to said first input of said exclusive OR gate, and bit 3 is said second bit location that is coupled to said second input of said exclusive OR gate.

8. The invention of claim 5 further comprising a flip-flop having a data input coupled to the output of said first combinatorial circuitry, having a clock input coupled to receive said clock signal, and an output coupled to said set input of said shift register.

9. A method for resetting a computer system upon the occurrence of a software runaway situation, comprising the step of counting a clock signal by means of a counter, characterized in that said counting is accomplished by steps comprising:

shifting data into a shift register having n bit locations via a data input under the control of a clock signal received via a clock input;

and feeding back a data signal to said data input when a given pattern of bits is located in said shift register, whereby a 2.sup.n -1 counter is implemented for resetting said computer system;

and wherein said counter comprises test circuitry that logically combines the data in the n bit positions of the counter to form an output signal that indicates that a desired pattern has been achieved when each bit of the shift register has made all possible state transitions in a number of clock cycles less than 2.sup.n -1.

10. The invention of claim 9 whereby feeding back said data signal is accomplished by exclusively ORing a first input coupled to a first bit location and a second input coupled to a second bit location, and providing the resulting signal to said data input.

11. The invention of claim 10 wherein n=20 arranged from bit 19 nearest the data input to bit 0 farthest from the data input, and wherein bit 0 is said first bit location, and bit 3 is said second bit location.

12. The invention of claim 9 further comprising the step of programmably dividing said data signal from said shift register in order to implement said resetting of said computer system.