Patent US6850443 - Wear leveling techniques for flash EEPROM systems

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

Inventors: Karl M. J. Lofgren, Robert D. Norman, Gregory B. Thelin, Anil Gupta
Original Assignees: SanDisk Corporation, Western Digital Corporation
Primary Examiner: Viet Q. Nguyen
Attorney: Parsons Hsue & de Runtz LLP
Current U.S. Classification: 365/185.29; 365/185.11; 365/185.33; 365/218
International Classification: G11C/1100

View patent at USPTO
Search USPTO Assignment Database
Download USPTO Public PAIR data

Citations

Cited Patent	Filing date	Issue date	Original Assignee	Title
US4093985	Nov 5, 1976	Jun 6, 1978	North Electric Company	Memory sparing arrangement
US4430727	Nov 10, 1981	Feb 7, 1984	International Business Machines Corp.	Storage element reconfiguration
US4528683	May 25, 1982	Jul 9, 1985	VDO Adolf Schindling AG	Circuit for storing a multi-digit decimal numerical value of the distance traversed by a vehicle
US4530054	Mar 3, 1982	Jul 16, 1985	Sperry Corporation	Processor-addressable timestamp for indicating oldest written-to cache entry not copied back to bulk memory
US4562532	May 24, 1982	Dec 31, 1985	Fujitsu Limited	Main storage configuration control system
US4563752	Jun 6, 1983	Jan 7, 1986	U.S. Philips Corporation	Series/parallel/series shift register memory comprising redundant parallel-connected storage registers, and display apparatus comprising a picture memory thus organized
US4608671	May 2, 1983	Aug 26, 1986	Hitachi, Ltd.	Buffer storage including a swapping circuit
US4612640	Feb 21, 1984	Sep 16, 1986	Seeq Technology, Inc.	Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
US4616311	Apr 29, 1985	Oct 7, 1986	Tokyo Shibaura Denki Kabushiki Kaisha	Data processing system
US4638457	May 28, 1982	Jan 20, 1987	Siemens Aktiengesellschaft	Method and apparatus for the non-volatile storage of the count of an electronic counting circuit
US4663770	Feb 24, 1986	May 5, 1987	Hughes Microlectronics Limited	Non-volatile counting circuit and method which provides for extended counter life
US4682287	Aug 28, 1984	Jul 21, 1987	Nippondenso Co., Ltd.	Electronic odometer
US4718041	Jan 9, 1986	Jan 5, 1988	Texas Instruments Incorporated	EEPROM memory having extended life
US4803707	Dec 21, 1987	Feb 7, 1989	NCR Corporation	Nonvolatile electronic odometer with excess write cycle protection
US4899272	Oct 23, 1987	Feb 6, 1990	Chips & Technologies, Inc.	Addressing multiple types of memory devices
US4922456	Apr 29, 1988	May 1, 1990	Scientific-Atlanta, Inc.	Method of reducing wearout in a non-volatile memory with double buffer
US4924375	Oct 23, 1987	May 8, 1990	Chips and Technologies, Inc.	Page interleaved memory access
US4943962	Oct 28, 1988	Jul 24, 1990	Kabushiki Kaisha Toshiba	Nonvolatile semiconductor memory having page mode programming function
US4947410	Feb 23, 1989	Aug 7, 1990	General Motors Corporation Delco Electyronic Corp.	Method and apparatus for counting with a nonvolatile memory
US4953073	Feb 6, 1986	Aug 28, 1990	MIPS Computer Systems, Inc.	Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US5034926	Aug 10, 1989	Jul 23, 1991	Kabushiki Kaisha Toshiba	Non-volatile semiconductor memory
US5043940	Jul 17, 1989	Aug 27, 1991		Flash EEPROM memory systems having multistate storage cells
US5053990	Feb 17, 1988	Oct 1, 1991	Intel Corporation	Program/erase selection for flash memory
US5065364	Sep 15, 1989	Nov 12, 1991	Intel Corporation	Apparatus for providing block erasing in a flash EPROM
US5065564	Oct 25, 1990	Nov 19, 1991	Maschinenfabrik Alfred Schmermund GmbH & Co.	Apparatus for the formation of cigarette groups
US5095344	Jun 8, 1988	Mar 10, 1992		Highly compact EPROM and flash EEPROM devices
US5103411	Apr 5, 1990	Apr 7, 1992	Nippon Seiki Co., Ltd.	Electronic odometer wherein medium order digit data addresses locations which store high and low order digit data
US5134589	Jul 23, 1990	Jul 28, 1992	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device having a flash write function
US5138580	May 30, 1990	Aug 11, 1992	Gemplus Card International	Method for the erasure of memory cells, device designed to implement it, and use of said method in a device with non-supplied memory
US5155705	Aug 13, 1991	Oct 13, 1992	Fujitsu Limited Fujitsu VLSI Limited	Semiconductor memory device having flash write function
US5163021	Jul 22, 1991	Nov 10, 1992	SunDisk Corporation	Multi-state EEprom read and write circuits and techniques
US5168465	Jan 15, 1991	Dec 1, 1992		Highly compact EPROM and flash EEPROM devices
US5172338	Apr 11, 1990	Dec 15, 1992	Sundisk Corporation	Multi-state EEprom read and write circuits and techniques
US5193071	Mar 3, 1992	Mar 9, 1993	Digital Equipment Corporation	Memory apparatus for multiple processor systems
US5210716	Jul 23, 1990	May 11, 1993	Seiko Instruments Inc.	Semiconductor nonvolatile memory
US5222109	Dec 28, 1990	Jun 22, 1993	IBM Corporation	Endurance management for solid state files
US5245572	Jul 30, 1991	Sep 14, 1993	Intel Corporation	Floating gate nonvolatile memory with reading while writing capability
US5263003	Nov 12, 1991	Nov 16, 1993	Allen-Bradley Company, Inc.	Flash memory circuit and method of operation
US5267218	Mar 31, 1992	Nov 30, 1993	Intel Corporation	Nonvolatile memory card with a single power supply input
US5268870	Aug 6, 1990	Dec 7, 1993		Flash EEPROM system and intelligent programming and erasing methods therefor
US5270979	Mar 15, 1991	Dec 14, 1993	SunDisk Corporation	Method for optimum erasing of EEPROM
US5272669	Feb 20, 1991	Dec 21, 1993	Sundisk Corporation	Method and structure for programming floating gate memory cells
US5280447	Jun 19, 1992	Jan 18, 1994	Intel Corporation	Floating gate nonvolatile memory with configurable erasure blocks
US5295255	Feb 22, 1991	Mar 15, 1994	Electronic Professional Services, Inc.	Method and apparatus for programming a solid state processor with overleaved array memory modules
US5297148	Oct 20, 1992	Mar 22, 1994	SunDisk Corporation	Flash eeprom system
US5303198	Jul 5, 1991	Apr 12, 1994	Fuji Photo Film Co., Ltd.	Method of recording data in memory card having EEPROM and memory card system using the same
US5341489	Apr 14, 1992	Aug 23, 1994	Eastman Kodak Company	Memory card with programmable interleaving
US5357473	Oct 6, 1993	Oct 18, 1994	Mitsubishi Denki Kabushiki Kaisha	Semiconductor storage system including defective bit replacement
US5371876	Oct 14, 1993	Dec 6, 1994	Intel Corporation	Computer system with a paged non-volatile memory
US5388083	Mar 26, 1993	Feb 7, 1995	Cirrus Logic, Inc.	Flash memory mass storage architecture
US5430859	Jul 26, 1991	Jul 4, 1995	Sundisk Corporation	Solid state memory system including plural memory chips and a serialized bus
US5544118	Mar 7, 1995	Aug 6, 1996		Flash EEPROM system cell array with defect management including an error correction scheme
US5548554	Dec 28, 1994	Aug 20, 1996	SGS-Thompson Microelectronics, S.r.l.	Integrated programming circuitry for an electrically programmable semiconductor memory device with redundancy
US5630093	Apr 19, 1996	May 13, 1997	Intel Corporation	Disk emulation for a non-volatile semiconductor memory utilizing a mapping table
US5663901	Sep 12, 1995	Sep 2, 1997	Sandisk Corporation	Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
US5726937	May 21, 1996	Mar 10, 1998	Norand Corporation	Flash memory system having memory cache
US5930167	Jul 30, 1997	Jul 27, 1999	SanDisk Corporation	Multi-state non-volatile flash memory capable of being its own two state write cache
US6081447	Mar 5, 1999	Jun 27, 2000	Western Digital Corporation SanDisk Corporation	Wear leveling techniques for flash EEPROM systems
US6230233	Sep 13, 1991	May 8, 2001	Sandisk Corporation	Wear leveling techniques for flash EEPROM systems
US6594183	Jun 30, 1998	Jul 15, 2003	SanDisk Corporation Western Digital Corporation	Wear leveling techniques for flash EEPROM systems

Referenced by

Citing Patent	Filing date	Issue date	Original Assignee	Title
US7353325	Jan 3, 2005	Apr 1, 2008	SanDisk Corporation	Wear leveling techniques for flash EEPROM systems
US7361188	Apr 8, 2005	Apr 22, 2008	Exelys, LLC	Portable cardiac monitor
US7451264	Apr 13, 2006	Nov 11, 2008	SanDisk Corporation	Cycle count storage methods
US7467253	Apr 13, 2006	Dec 16, 2008	SanDisk Corporation	Cycle count storage systems
US7474914	Apr 8, 2005	Jan 6, 2009	Exelys, LLC	Portable cardiac monitor including a range limiter
US7515471	Oct 19, 2006	Apr 7, 2009	MOSAID Technologies Incorporated	Memory with output control
US7529149	Dec 12, 2006	May 5, 2009	MOSAID Technologies Incorporated	Memory system and method with serial and parallel modes
US7549034	Nov 10, 2005	Jun 16, 2009	International Business Machines Corporation	Redistribution of memory to reduce computer system power consumption
US7551492	Mar 8, 2007	Jun 23, 2009	Mosaid Technologies, Inc.	Non-volatile semiconductor memory with page erase
US7577059	Feb 27, 2007	Aug 18, 2009	Mosaid Technologies Incorporated	Decoding control with address transition detection in page erase function
US7636258	Dec 12, 2007	Dec 22, 2009	Qimonda Flash GmbH	Integrated circuits, memory controller, and memory modules
US7646636	Jul 27, 2007	Jan 12, 2010	MOSAID Technologies Incorporated	Non-volatile memory with dynamic multi-mode operation
US7650480	Aug 28, 2006	Jan 19, 2010	Hitachi, Ltd.	Storage system and write distribution method
US7652922	Dec 30, 2005	Jan 26, 2010	MOSAID Technologies Incorporated	Multiple independent serial link memory
US7689762	May 3, 2007	Mar 30, 2010	ATMEL Corporation	Storage device wear leveling
US7719892	Jul 25, 2008	May 18, 2010	MOSAID Technologies Incorproated	Flash memory device with data output control
US7747833	Dec 22, 2006	Jun 29, 2010	Mosaid Technologies Incorporated	Independent link and bank selection
US7751272	Feb 5, 2008	Jul 6, 2010	MOSAID Technologies Incorporated	Semiconductor device and method for selection and de-selection of memory devices interconnected in series
US7774537	Feb 13, 2008	Aug 10, 2010	Mosaid Technologies Incorporated	Apparatus and method of page program operation for memory devices with mirror back-up of data
US7778107	Apr 1, 2009	Aug 17, 2010	Mosaid Technologies Incorporated	Decoding control with address transition detection in page erase function
US7796462	Feb 21, 2008	Sep 14, 2010	Mosaid Technologies Incorporated	Data flow control in multiple independent port
US7802064	Mar 29, 2007	Sep 21, 2010	Mosaid Technologies Incorporated	Flash memory system control scheme
US7804718	Jul 18, 2007	Sep 28, 2010	MOSAID Technologies Incorporated	Partial block erase architecture for flash memory
US7817470	Nov 23, 2007	Oct 19, 2010	MOSAID Technologies Incorporated	Non-volatile memory serial core architecture
US7818464	Dec 6, 2006	Oct 19, 2010	Mosaid Technologies Incorporated	Apparatus and method for capturing serial input data
US7826294	Nov 21, 2008	Nov 2, 2010	Mosaid Technologies Incorporated	Memory with output control
US7852582	Nov 21, 2007	Dec 14, 2010	Nokia Corporation	Method for determining wear of a data storage medium and data storage device
US7853727	Mar 28, 2007	Dec 14, 2010	MOSAID Technologies Incorporated	Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection
US7872921	May 28, 2009	Jan 18, 2011	MOSAID Technologies Incorporated	Non-volatile semiconductor memory with page erase
US7904639	Aug 17, 2007	Mar 8, 2011	Mosaid Technologies Incorporated	Modular command structure for memory and memory system
US7908423	Jan 11, 2008	Mar 15, 2011	Silicon Motion, Inc.	Memory apparatus, and method of averagely using blocks of a flash memory
US7908429	Jul 8, 2010	Mar 15, 2011	Mosaid Technologies Incorporated	Apparatus and method of page program operation for memory devices with mirror back-up of data
US7913128	Feb 8, 2008	Mar 22, 2011	MOSAID Technologies Incorporated	Data channel test apparatus and method thereof
US7940572	Jun 20, 2008	May 10, 2011	MOSAID Technologies Incorporated	NAND flash memory having multiple cell substrates
US7945755	Apr 9, 2010	May 17, 2011	MOSAID Technologies Incorporated	Independent link and bank selection
US7970983	Oct 14, 2007	Jun 28, 2011	SanDisk IL Ltd.	Identity-based flash management
US7983099	Oct 24, 2008	Jul 19, 2011	MOSAID Technologies Incorporated	Dual function compatible non-volatile memory device
US7991925	Feb 4, 2008	Aug 2, 2011	Mosaid Technologies Incorporated	Apparatus and method for identifying device types of series-connected devices of mixed type
US7995401	Sep 22, 2010	Aug 9, 2011	MOSAID Technologies Incorporated	Non-volatile semiconductor memory with page erase
US7996725	Nov 14, 2008	Aug 9, 2011	Nokia Corporation	Providing protection for a memory device
US8000144	Mar 26, 2010	Aug 16, 2011	MOSAID Technologies Incorporated	Method and system for accessing a flash memory device
US8010709	Jan 19, 2007	Aug 30, 2011	MOSAID Technologies Incorporated	Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US8010710	Mar 28, 2007	Aug 30, 2011	MOSAID Technologies Incorporated	Apparatus and method for identifying device type of serially interconnected devices
US8015346	Mar 18, 2008	Sep 6, 2011	A-Data Technology Co., Ltd.	Memory system having hybrid density memory and methods for wear-leveling management and file distribution management thereof
US8037235	Dec 18, 2008	Oct 11, 2011	Mosaid Technologies Incorporated	Device and method for transferring data to a non-volatile memory device
US8045377	Dec 10, 2009	Oct 25, 2011	MOSAID Technologies Incorporated	Non-volatile memory with dynamic multi-mode operation
US8046527	Feb 12, 2008	Oct 25, 2011	Mosaid Technologies Incorporated	Apparatus and method for using a page buffer of a memory device as a temporary cache
US8051241	May 7, 2009	Nov 1, 2011	Seagate Technology LLC	Wear leveling technique for storage devices
US8060691	Feb 7, 2011	Nov 15, 2011	MOSAID Technologies Incorporated	Apparatus and method of page program operation for memory devices with mirror back-up of data
US8069328	Nov 29, 2006	Nov 29, 2011	MOSAID Technologies Incorporated	Daisy chain cascade configuration recognition technique
US8086785	Jul 6, 2007	Dec 27, 2011	Mosaid Technologies Incorporated	System and method of page buffer operation for memory devices
US8090899	Mar 4, 2009	Jan 3, 2012	Western Digital Technologies, Inc.	Solid state drive power safe wear-leveling
US8122179	Dec 14, 2007	Feb 21, 2012	Silicon Motion, Inc.	Memory apparatus and method of evenly using the blocks of a flash memory
US8122202	Aug 22, 2007	Feb 21, 2012		Reduced pin count interface
US8139390	Jul 8, 2008	Mar 20, 2012	MOSAID Technologies Incorporated	Mixed data rates in memory devices and systems
US8140737	Jan 30, 2007	Mar 20, 2012	Skymedi Corporation	Method for enhancing life cycle of memory
US8159893	Aug 6, 2010	Apr 17, 2012	MOSAID Technologies Incorporated	Data flow control in multiple independent port
US8169849	Mar 27, 2009	May 1, 2012	Mosaid Technologies Incorporated	Memory system and method with serial and parallel modes
US8176236	Feb 18, 2010	May 8, 2012	TDK Corporation	Memory controller, memory system with memory controller, and method of controlling flash memory
US8194481	Dec 17, 2009	Jun 5, 2012	Mosaid Technologies Incorporated	Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation
US8195839	Sep 28, 2010	Jun 5, 2012	Mosaid Technologies Incorporated	Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection
US8195978	May 18, 2009	Jun 5, 2012	Fusion-IO. Inc.	Apparatus, system, and method for detecting and replacing failed data storage
US8199598	Sep 15, 2010	Jun 12, 2012	MOSAID Technologies Incorporated	Memory with output control
US8200891	Feb 8, 2010	Jun 12, 2012	TDK Corporation	Memory controller, memory system with memory controller, and method of controlling flash memory
US8200892	Feb 8, 2010	Jun 12, 2012	TDK Corporation	Memory controller, memory system with memory controller, and method of controlling flash memory
US8209466	Dec 16, 2008	Jun 26, 2012	Intel Corporation	Methods and systems to allocate addresses in a high-endurance/low-endurance hybrid flash memory
US8213229	Aug 22, 2008	Jul 3, 2012	HGST Netherlands, B.V.	Error control in a flash memory device
US8213240	Jun 27, 2011	Jul 3, 2012	Mosaid Technologies Incorporated	Non-volatile semiconductor memory with page erase
US8230129	Jun 24, 2011	Jul 24, 2012	MOSAID Technologies Incorporated	Apparatus and method for identifying device types of series-connected devices of mixed type
US8239612	Sep 26, 2008	Aug 7, 2012	TDK Corporation	Memory controller, flash memory system with memory controller, and control method of flash memory
US8244995	Oct 30, 2008	Aug 14, 2012	Dell Products L.P.	System and method for hierarchical wear leveling in storage devices

Claims

1. A method of managing operation of an EEPROM mass storage system having at least one integrated circuit containing memory cells divided into a number of groups of memory cells that are erased together and which are then rewritten with data, comprising the steps of:

monitoring a number of rewrite cycles directed at the groups of cells,

determining when a predetermined imbalance exists in a number of rewrite cycles directed at the groups of cells,

in response to such an imbalance, reassigning at least one of the groups of cells to receive data designated for at least another of the groups of cells in order to correct the imbalance during further rewrite cycles, and

wherein data are subsequently rewritten in said at least another of the groups of cells.

2. The method according to claim 1 wherein the monitoring step includes accumulating a number of rewrite cycles of individual groups by logical group addresses applied to the storage system before any conversion to physical group addresses.

3. The method according to claim 1 wherein the monitoring step includes accumulating a number of rewrite cycles of individual groups by physical group addresses that are translated from logical group addresses applied to the storage system.

4. The method according to claim 1 wherein the imbalance determining step includes the steps of:

identifying one of said groups having a highest number of rewrite cycles,

determining a total number of group rewrite cycles that the memory could accommodate if all of said groups had the same number of rewrite cycles as said one group, and

comparing that total determined number with a total number of rewrite cycles actually directed to said groups.

5. The method according to claim 1 wherein the imbalance determining step includes the steps of:

identifying a first of said groups having a higher number of rewrite cycles than others of said groups,

identifying a second of said groups having a lower number of rewrite cycles than others of said groups, and

determining whether a difference between the number of rewrite cycles of said first and second groups exceeds a predetermined threshold.

6. The method according to claim 1 which additionally comprises the step of swapping stored data among said at least one and said at least another group of cells.

7. The method according to claim 6 wherein said swapping step includes use of another group of cells to which data is transferred from either said at least one or said at least another group of cells.

8. A method of managing operation of a rewritable non-volatile mass storage system divided into a number of groups of memory cells which are periodically rewritten with new data, wherein a target endurance limit of a maximum number of rewrite cycles is designated for the memory cells, comprising:

monitoring a number of rewrite cycles directed at the groups of memory cells,

determining, before any of the individual groups of memory cells reaches the target endurance limit of the maximum number of rewrite cycles, when a predetermined imbalance exists in a number of rewrite cycles experienced among the groups of memory cells, and

in response to determining that such an imbalance exists,

copying stored data from at least one of the groups of memory cells into at least another of the groups of memory cells, and

reassigning said at least another of the groups of memory cells to receive data designated for said at least one of the groups of memory cells in order to correct the imbalance during further rewrite cycles.

9. The method according to claim 8 wherein monitoring the number of rewrite cycles includes accumulating a number of rewrite cycles of individual groups by logical group addresses applied to the storage system before conversion to physical group addresses.

10. The method according to claim 8 wherein monitoring the number of rewrite cycles includes accumulating a number of rewrite cycles of individual groups by physical group addresses that are translated from logical group addresses applied to the storage system.

11. The method according to claim 8 wherein determining when a predetermined imbalance exists includes: