Generalized digital multiplier and digital filter using said multiplier

1. Generalized digital multiplier able to calculate a quantity P of form: ##EQU17## in which the terms a.sub.i are binary words corresponding to N given coefficients and the terms x.sub.i are binary words of B bits corresponding to N variable signals, said generalized digital multiplier being characterized in that it comprises:

N shift registers (RD.sub.0, . . . RD.sub.N-1) with parallel word input on B bits and series bit output, the ith register (RD.sub.i) containing the B bits of the binary word x.sub.i,

N conditional adders (AdC.sub.0, . . . , AdC.sub.N-1) each provided with a data input, a data output and a control input, the control input (ec.sub.i) of the ith conditional adder (AdC.sub.i) being connected to the output of the ith shift register, (RD.sub.i), the data input (ed.sub.i) and the data output (sd.sub.i) of the ith conditional adder (AdC.sub.i) being respectively connected to the data ouput of the (i-1) ith conditional adder and to the data input of the (i+1) ith conditional adder, said ith conditional adder (AdC.sub.i) incorporating the term a.sub.i and adding the latter to the signal received on its data input, conditionally with respect to the value of the jth bit x.sub.ij of the word x.sub.i, said bit being received on the control input (ec.sub.i),

an adder accumulator (AdAc) provided with first and second data inputs, (Ed.sub.1, Ed.sub.2) the first data input (Ed.sub.1) being connected to the output (sd.sub.N-1) of the Nth conditional adder, (AdC.sub.N-1), said adder accumulator (AdAc) also having a data output (Sd) connected to the second data input (Ed.sub.2) of said adder accumulator (AdAc) following the shifting of the bits by one position,

a clock circuit (H) for the control in parallel of the shifting of the B bits contained in the N series registers (RD.sub.0, . . . , RD.sub.N-1) and passing the order j from 0 to B-1 and

the sought quantity P being supplied on the data output of the adder accumulator (AdAc) every B clock stroke.

2. Digital multiplier according to claim 1, characterized in that each conditional adder (AdC.sub.i) is constituted by an adder (Ad.sub.i), and a multiplexer (MX.sub.i) with two data inputs (e.sub.i, e'.sub.i) respectively connected to the input and output of the adder (Ad.sub.i) and a control input (Ec.sub.i) connected to the output of the shift register of the same order (RD.sub.i) and receiving a bit (x.sub.ij).

3. Non-recursive digital filter for the calculation of an expression in form: ##EQU18## in which the terms a.sub.i are binary words corresponding to N given coefficients and the terms x.sub.i are binary words of B bits corresponding to N variable signals, said filter comprising:

a general input register with N shift registers (REG.sub.n, . . . , REG.sub.n-N+1) of B bits, each register having a parallel input on B bits and a first parallel output on B bits, said registers being interconnected in parallel by said parallel inputs-outputs, each register also having a second parallel output, said shift registers (REG.sub.n, . . . , REG.sub.n-N+1) operating at a frequency fs' and

a digital multiplier comprising:

N shift registers (RD.sub.0, . . . , RD.sub.N-1) with parallel word input on B bits and series bit output, the ith register (RD.sub.i) containing the B bits of the binary word x.sub.i, said parallel word input of a ith register (RD.sub.i) being connected to said second output of the ith register (REG.sub.i) of said general input register, said shift register (RD.sub.0, . . . , RD.sub.N-1) operating at a frequency f.sub.r,

N conditional adders (AdC.sub.0, . . . , AdC.sub.N-1) each provided with a data input, a data output (ec.sub.i) of the ith conditional adder (AdC.sub.i) being connected to the output of the ith register, (RD.sub.i), the data input (ed.sub.i) and the data output (sd.sub.i) of the ith conditional adder (AdC.sub.i) being respectively connected to the data output of the (i-1)th conditional adder and to the data input of the (i+1)th conditional adder, said ith conditional adder (AdC.sub.i) incorporating the term a.sub.i and adding the latter to the signal received on its data input, conditionally with respect to the value of the jth bit x.sub.ij of the word x.sub.j, said bit being received on the control input (ec.sub.i), said conditional adders (AdC.sub.0, . . . , Adc.sub.N-1) operating at a calculating frequency f.sub.c,

an adder accumulator (AdAc) provided with first and second data inputs, (Ed.sub.1, Ed.sub.2) the first data input (Ed.sub.1) being connected to the output (sd.sub.N-1), sid adder accumulator (AdAc) also having a data output (Sd) connected to the second data input (Ed.sub.2) of said adder accumulator (AdAc) following the shifting of the bits by one position,

a clock circuit (H) for the control in parallel of the shifting of the B bits contained in the N series registers (RD.sub.0, . . . , RD.sub.N-1) and passing the order j from 0 to B-1 and the sought quantity P being supplied on the data output of the adder accumulator (AdAc) every B clock stroke.

4. Digital filter according to claim 3, wherein said f.sub.r =f.sub.s and f.sub.c =Bf.sub.s.

5. Digital filter according to claim 3, further including a means for operating with subsampling of a factor M and f.sub.r =f.sub.s /M and f.sub.c =BF.sub.s /M.

6. A digital filter comprising L filters (F.sub.1, F.sub.2, etc . . . ) in parallel, said L filters having a common input (E) receiving samples (x.sub.n, x.sub.n-1, etc.) at a signal frequency f.sub.s, each filter only recording the samples at a frequency f.sub.r =f.sub.s /L at different times between individual filters and shifted by (Ts/L), in which Ts designates the period corresponding to frequency F.sub.s, said filters having outputs being connected at a single output constituting an output of said digital filter, each filter calculating an expression in form: ##EQU19## in which the terms a.sub.i are binary words corresponding to N given coefficients and the terms x.sub.i are binary words of B bits corresponding to N variable signals, each filter comprising:

a general input register with N shift registers (REG.sub.n, . . . , REG.sub.n-N+1) of B bits, each register having a parallel input on B bits and a first parallel output on B bits, said registers being interconnected in parallel by said parallel inputs-outputs, each register also having a second parallel output, said shift registers (REG.sub.n, . . . , REG.sub.n-N+1) operating at a frequency f.sub.s,

a digital multiplier comprising:

N shift registers (RD.sub.0, . . . , RD.sub.N-1) with parallel word input on B bits and series bit output, the ith register (RD.sub.i) containing the B bits of the binary word x.sub.i, said parallel word input of a ith register (RD.sub.i) being connected to said second output of the ith register (REG.sub.i) of said general input register, said shift register (RD.sub.0, . . . , RD.sub.N-1 operating at a frequency f.sub.r,

N conditional adders (AdC.sub.0, . . . , AdC.sub.N-1) each provided with a data input, a data output and a control input, the control input (ec.sub.i) of the ith conditional adder (AdC.sub.i) being connected to the output of the ith register, (RD.sub.i), the data input (ed.sub.i) and the data output (sd.sub.i) of the ith conditional adder (AdC.sub.i) being respectively connected to the data output of the (i-1)th conditional adder and to the data input of the (i+1)th conditional adder, said ith conditional adder (AdC.sub.i) incorporating the term a.sub.i and adding the latter to the signal received on its data input, conditionally with respect to the value of the jth bit x.sub.ij of the word x.sub.j, said bit being received on the control input (ed.sub.i), said conditional adders (AdC.sub.0, . . . , AdC.sub.N-1) operating at a calculating frequency f.sub.c,

an adder accumulator (AdAc) provided with first and second data inputs, (Ed.sub.1, Ed.sub.2) the first data input (Ed.sub.1) being connected to the output (sd.sub.N-1), said adder accumulator (AdAc) also having a data output (Sd) connected to the second data input (ED.sub.2) of said adder accumulator (AdAc) following the shifting of the bits by one position,

a clock circuit (H) for the control in parallel of the shifting of the B bits contained in the N series registers (RD.sub.0', . . . , RD.sub.N-1) and passing the order j from 0 to B-1 and the sought quantity P being supplied on the data output of the adder accumulator (AdAc) every B clock stroke.