Bus mastering debugging system for integrated circuits

1. An integrated circuit comprising:

a general purpose bus;

a bus master device coupled to the general purpose bus;

a debugging unit coupled to the general purpose bus, wherein the debugging unit is configurable to operate as a bus master of the general purpose bus.

2. The integrated circuit of claim 1, wherein the bus master device is a microprocessor.

3. The integrated circuit of claim 1, wherein the bus master device comprises a plurality of freezeable storage elements coupled to the debugging unit.

4. The integrated circuit of claim 1, wherein the bus master devices comprises a plurality of storage elements mapped in an address space of the general purpose bus.

5. The integrated circuit of claim 4, wherein the debugging unit can read from and write to the plurality of storage elements.

6. The integrated circuit of claim 1, further comprising a bus device coupled to the general purpose bus.

7. The integrated circuit of claim 6, wherein the bus device is a field programmable gate array having configurable logic circuits and configuration memories.

8. The integrated of circuit claim 7, wherein the configuration memories are mapped in an address space of the general purpose bus.

9. The integrated circuit of claim 7, wherein the configurable logic circuits comprises a plurality of storage elements mapped in an address space of the general purpose bus.

10. The integrated circuit of claim 6, further comprising a breakpoint unit coupled to the general purpose bus, the bus master device, and the bus device, wherein the breakpoint unit can freeze the bus master device and the bus device.

11. The integrated circuit of claim 10, wherein the break point unit is coupled to the bus device through a clock control circuit.

12. The integrated circuit of claim 1, further comprising:

a memory device coupled to the general purpose bus; and

a DMA unit coupled to the general purpose bus.

13. A method of debugging an integrated circuit, the method comprising:

freezing a bus master device within the integrated circuit;

configuring a debugging unit within the integrated circuit to operate as a bus master on the general purpose bus; and

reading storage elements of the integrated circuit using a general purpose bus within the integrated circuit.

14. The method of claim 13, further comprising programming a breakpoint unit to freeze the bus master device.

15. The method of claim 13, further comprising unfreezing the bus master device.

16. The method of claim 13, wherein the freezing the bus master device comprises neutralizing a clock signal to the bus master device.

17. The method of claim 13, wherein the freezing the bus master device comprises driving a freeze signal of a freezeable storage element to an active logic level.

18. The method of claim 13, further comprising freezing a bus device.

19. The method of claim 18, wherein the freezing a bus device comprises neutralizing a clock signal to the bus device.