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 vhdl  
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Jasper Design Automation Enables 100% Actual Coverage for VHDL Users
Business Wire (press release) - Mar 8 2005   
Reminder - Call for Registrations, Accellera Hosts a Free Power Lunch With Interoperable EDA Tool Demonstrations and a VHDL Tutorial With the IEEE at DATE
Market Wire (press release) - Apr 16 2007   
Accellera Supports VHDL 4.0 Standard and IEEE 1076 TM -2008 Ratification
Market Wire (press release) - Feb 20 2008   
Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI)
StreetInsider.com (subscription) - Feb 25 2008   
Aldec Releases ALINT 2008.10 Supporting Mixed VHDL and Verilog Design Rule Checking
Centre Daily Times - Dec 8 2008   
RealTime - Oasys Design Systems Adds VHDL Support to RealTime Designer
Ad-Hoc-News (Pressemitteilung) - Nov 17 2009   
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