SoC and IP Design Engineer, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
- Experience with microarchitecture and specifications.
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
- Experience in logic design and debug with Design Verification (DV).
Preferred qualifications:
- Experience with design sign off and quality tools (Lint, CDC, VCLP etc.).
- Experience with a scripting language like Python or Perl.
- Knowledge in one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
- Knowledge of SOC architecture and assertion-based formal verification.
- Knowledge of high performance and low power design techniques.
About the job
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC and SoC IP’s from Plan of Record (POR) to Production. This includes creating SoC Level microarchitecture definitions, RTL coding and all RTL quality checks. You will also have the opportunity to contribute to Design flow and Methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical challenges and develop/define design options for performance, power and area.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities
- Define the SoC/Block microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform RTL development (coding and debug in Verilog, SystemVerilog).
- Function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
- Contribute to verification test plan and coverage analysis of block and SOC-level.
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